Logic/resistive-switching hybrid transistor for two-bit-per-cell storage

Shih Chieh Wu; Chieh Lo; Tuo-Hung Hou

doi:10.1109/VLSI-TSA.2012.6210103

Logic/resistive-switching hybrid transistor for two-bit-per-cell storage

Shih Chieh Wu, Chieh Lo, Tuo-Hung Hou^*

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Various bias schemes in the RS-TFT have been comprehensively investigated. As shown in Table I, the V _D-biased bipolar RS is superior for the logic/RS hybrid operation with the ability of two-bit-per-cell storage because of its large program margin, localized filament location, negligible V _TH shift, and suppressed gate leakage current. In comparison with other embedded memory technologies, the proposed RS-TFT in this work not only is compatible with logic CMOS technology, but also provides comparable memory performance with a very competitive cell size.

Original language	English
Title of host publication	2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012 - Proceedings of Technical Papers
DOIs	https://doi.org/10.1109/VLSI-TSA.2012.6210103
State	Published - 2012
Event	2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012 - Hsinchu, Taiwan Duration: 23 Apr 2012 → 25 Apr 2012

Publication series

Name	International Symposium on VLSI Technology, Systems, and Applications, Proceedings
ISSN (Print)	1930-8868

Conference

Conference	2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012
Country/Territory	Taiwan
City	Hsinchu
Period	23/04/12 → 25/04/12

Access to Document

10.1109/VLSI-TSA.2012.6210103

Cite this

Wu, S. C., Lo, C., & Hou, T.-H. (2012). Logic/resistive-switching hybrid transistor for two-bit-per-cell storage. In 2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012 - Proceedings of Technical Papers Article 6210103 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). https://doi.org/10.1109/VLSI-TSA.2012.6210103

@inproceedings{cdf29c9eac424d779a1093c83bf2f37c,

title = "Logic/resistive-switching hybrid transistor for two-bit-per-cell storage",

abstract = "Various bias schemes in the RS-TFT have been comprehensively investigated. As shown in Table I, the V D-biased bipolar RS is superior for the logic/RS hybrid operation with the ability of two-bit-per-cell storage because of its large program margin, localized filament location, negligible V TH shift, and suppressed gate leakage current. In comparison with other embedded memory technologies, the proposed RS-TFT in this work not only is compatible with logic CMOS technology, but also provides comparable memory performance with a very competitive cell size.",

author = "Wu, {Shih Chieh} and Chieh Lo and Tuo-Hung Hou",

year = "2012",

doi = "10.1109/VLSI-TSA.2012.6210103",

language = "English",

isbn = "9781457720840",

series = "International Symposium on VLSI Technology, Systems, and Applications, Proceedings",

booktitle = "2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012 - Proceedings of Technical Papers",

note = "2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012 ; Conference date: 23-04-2012 Through 25-04-2012",

}

Wu, SC, Lo, C & Hou, T-H 2012, Logic/resistive-switching hybrid transistor for two-bit-per-cell storage. in 2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012 - Proceedings of Technical Papers., 6210103, International Symposium on VLSI Technology, Systems, and Applications, Proceedings, 2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012, Hsinchu, Taiwan, 23/04/12. https://doi.org/10.1109/VLSI-TSA.2012.6210103

Logic/resistive-switching hybrid transistor for two-bit-per-cell storage. / Wu, Shih Chieh; Lo, Chieh; Hou, Tuo-Hung.
2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012 - Proceedings of Technical Papers. 2012. 6210103 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Logic/resistive-switching hybrid transistor for two-bit-per-cell storage

AU - Wu, Shih Chieh

AU - Lo, Chieh

AU - Hou, Tuo-Hung

PY - 2012

Y1 - 2012

N2 - Various bias schemes in the RS-TFT have been comprehensively investigated. As shown in Table I, the V D-biased bipolar RS is superior for the logic/RS hybrid operation with the ability of two-bit-per-cell storage because of its large program margin, localized filament location, negligible V TH shift, and suppressed gate leakage current. In comparison with other embedded memory technologies, the proposed RS-TFT in this work not only is compatible with logic CMOS technology, but also provides comparable memory performance with a very competitive cell size.

AB - Various bias schemes in the RS-TFT have been comprehensively investigated. As shown in Table I, the V D-biased bipolar RS is superior for the logic/RS hybrid operation with the ability of two-bit-per-cell storage because of its large program margin, localized filament location, negligible V TH shift, and suppressed gate leakage current. In comparison with other embedded memory technologies, the proposed RS-TFT in this work not only is compatible with logic CMOS technology, but also provides comparable memory performance with a very competitive cell size.

UR - http://www.scopus.com/inward/record.url?scp=84863655787&partnerID=8YFLogxK

U2 - 10.1109/VLSI-TSA.2012.6210103

DO - 10.1109/VLSI-TSA.2012.6210103

M3 - Conference contribution

AN - SCOPUS:84863655787

SN - 9781457720840

T3 - International Symposium on VLSI Technology, Systems, and Applications, Proceedings

BT - 2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012 - Proceedings of Technical Papers

T2 - 2012 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2012

Y2 - 23 April 2012 through 25 April 2012

ER -

Logic/resistive-switching hybrid transistor for two-bit-per-cell storage

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this