LOG-EXP still image compression chip design

Sheng-Chieh Huang*, Liang Gee Chen

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

1 Scopus citations

Abstract

In this paper, a fully pipelined single chip is proposed for the LOG-EXP still image compression. The design of the LOG-EXP image compression focus on the high compression ratio of the complex texture (e.g. benchmark image baboon) and high quality image, especially the PSNR requirement above 36. In comparison with the JPEG compression result (bpp = 0.99, PSNR = 26.9), this compression algorithm uses less bpp (bpp = 0.87) to get higher image quality (PSNR=36.38) for the benchmark image baboon. The entire LOG-EXP image compression system can be implemented on a single chip to yield a clock rate of 175 MHz which allow an input rate of 30 frames per second for 1024 × 1024 color images.

Original languageEnglish
Pages (from-to)156-157
Number of pages2
JournalDigest of Technical Papers - IEEE International Conference on Consumer Electronics
DOIs
StatePublished - 1 Dec 1999
EventProceedings of the 1999 IEEE International Conference on Consumer Electronics, ICCE'99 - Los Angeles, CA, USA
Duration: 22 Jun 199924 Jun 1999

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