Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits

Chih Chao Yang; Tung Ying Hsieh; Po-Tsang Huang; Kuan-Neng Chen; Wan Chi Wu; Shih Wei Chen; Chia He Chang; Chang Hong Shen; Jia Min Shieh; Chen-Ming Hu; Meng Chyi Wu; Wen Kuan Yeh

doi:10.1109/IEDM.2018.8614708

Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits

Chih Chao Yang, Tung Ying Hsieh, Po-Tsang Huang, Kuan-Neng Chen, Wan Chi Wu, Shih Wei Chen, Chia He Chang, Chang Hong Shen, Jia Min Shieh, Chen-Ming Hu, Meng Chyi Wu, Wen Kuan Yeh

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

19 Scopus citations

Abstract

A location-controlled-grain technique is presented for fabricating BEOL monolithic 3D FinFET ICs over SiO ₂ . The grain-boundary free Si FinFETs thus fabricated exhibit steep sub-threshold swing (<70mV/dec.), high driving currents (n-type: 363 μA/μm and p-type: 385 μ Aμm), and high I _on /I _off (>10 ⁶ ). According to simulation, the thickness of the interlayer dielectric plays an important role and shall be thicker than 250nm so that the sequential pulse laser crystallization process does not heat the bottom devices and interconnects to more than 400 °C.

Original language	English
Title of host publication	2018 IEEE International Electron Devices Meeting, IEDM 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	11.3.1-11.3.4
Number of pages	4
ISBN (Electronic)	9781728119878
DOIs	https://doi.org/10.1109/IEDM.2018.8614708
State	Published - 1 Dec 2018
Event	64th Annual IEEE International Electron Devices Meeting, IEDM 2018 - San Francisco, United States Duration: 1 Dec 2018 → 5 Dec 2018

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Volume	2018-December
ISSN (Print)	0163-1918

Conference

Conference	64th Annual IEEE International Electron Devices Meeting, IEDM 2018
Country/Territory	United States
City	San Francisco
Period	1/12/18 → 5/12/18

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10.1109/IEDM.2018.8614708

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Yang, C. C., Hsieh, T. Y., Huang, P.-T., Chen, K.-N., Wu, W. C., Chen, S. W., Chang, C. H., Shen, C. H., Shieh, J. M., Hu, C.-M., Wu, M. C., & Yeh, W. K. (2018). Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits. In 2018 IEEE International Electron Devices Meeting, IEDM 2018 (pp. 11.3.1-11.3.4). Article 8614708 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2018-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2018.8614708

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title = "Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits",

abstract = " A location-controlled-grain technique is presented for fabricating BEOL monolithic 3D FinFET ICs over SiO 2 . The grain-boundary free Si FinFETs thus fabricated exhibit steep sub-threshold swing (<70mV/dec.), high driving currents (n-type: 363 μA/μm and p-type: 385 μ Aμm), and high I on /I off (>10 6 ). According to simulation, the thickness of the interlayer dielectric plays an important role and shall be thicker than 250nm so that the sequential pulse laser crystallization process does not heat the bottom devices and interconnects to more than 400 °C. ",

author = "Yang, {Chih Chao} and Hsieh, {Tung Ying} and Po-Tsang Huang and Kuan-Neng Chen and Wu, {Wan Chi} and Chen, {Shih Wei} and Chang, {Chia He} and Shen, {Chang Hong} and Shieh, {Jia Min} and Chen-Ming Hu and Wu, {Meng Chyi} and Yeh, {Wen Kuan}",

year = "2018",

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doi = "10.1109/IEDM.2018.8614708",

language = "English",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "11.3.1--11.3.4",

booktitle = "2018 IEEE International Electron Devices Meeting, IEDM 2018",

address = "United States",

note = "64th Annual IEEE International Electron Devices Meeting, IEDM 2018 ; Conference date: 01-12-2018 Through 05-12-2018",

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Yang, CC, Hsieh, TY, Huang, P-T , Chen, K-N, Wu, WC, Chen, SW, Chang, CH, Shen, CH, Shieh, JM, Hu, C-M, Wu, MC & Yeh, WK 2018, Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits. in 2018 IEEE International Electron Devices Meeting, IEDM 2018., 8614708, Technical Digest - International Electron Devices Meeting, IEDM, vol. 2018-December, Institute of Electrical and Electronics Engineers Inc., pp. 11.3.1-11.3.4, 64th Annual IEEE International Electron Devices Meeting, IEDM 2018, San Francisco, United States, 1/12/18. https://doi.org/10.1109/IEDM.2018.8614708

Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits. / Yang, Chih Chao; Hsieh, Tung Ying; Huang, Po-Tsang et al.
2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 11.3.1-11.3.4 8614708 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2018-December).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits

AU - Yang, Chih Chao

AU - Hsieh, Tung Ying

AU - Huang, Po-Tsang

AU - Chen, Kuan-Neng

AU - Wu, Wan Chi

AU - Chen, Shih Wei

AU - Chang, Chia He

AU - Shen, Chang Hong

AU - Shieh, Jia Min

AU - Hu, Chen-Ming

AU - Wu, Meng Chyi

AU - Yeh, Wen Kuan

PY - 2018/12/1

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N2 - A location-controlled-grain technique is presented for fabricating BEOL monolithic 3D FinFET ICs over SiO 2 . The grain-boundary free Si FinFETs thus fabricated exhibit steep sub-threshold swing (<70mV/dec.), high driving currents (n-type: 363 μA/μm and p-type: 385 μ Aμm), and high I on /I off (>10 6 ). According to simulation, the thickness of the interlayer dielectric plays an important role and shall be thicker than 250nm so that the sequential pulse laser crystallization process does not heat the bottom devices and interconnects to more than 400 °C.

AB - A location-controlled-grain technique is presented for fabricating BEOL monolithic 3D FinFET ICs over SiO 2 . The grain-boundary free Si FinFETs thus fabricated exhibit steep sub-threshold swing (<70mV/dec.), high driving currents (n-type: 363 μA/μm and p-type: 385 μ Aμm), and high I on /I off (>10 6 ). According to simulation, the thickness of the interlayer dielectric plays an important role and shall be thicker than 250nm so that the sequential pulse laser crystallization process does not heat the bottom devices and interconnects to more than 400 °C.

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BT - 2018 IEEE International Electron Devices Meeting, IEDM 2018

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 64th Annual IEEE International Electron Devices Meeting, IEDM 2018

Y2 - 1 December 2018 through 5 December 2018

ER -

Yang CC, Hsieh TY, Huang PT , Chen KN, Wu WC, Chen SW et al. Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits. In 2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 11.3.1-11.3.4. 8614708. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM.2018.8614708

Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits

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