Local CDM ESD protection circuits for cross-power domains in 3D IC applications

Shih Hung Chen; Dimitri Linten; Mirko Scholz; Yu Ching Huang; Geert Hellings; Roman Boschke; Ming-Dou Ker; Guido Groeseneken

doi:10.1109/TDMR.2014.2320538

Local CDM ESD protection circuits for cross-power domains in 3D IC applications

Shih Hung Chen, Dimitri Linten, Mirko Scholz, Yu Ching Huang, Geert Hellings, Roman Boschke, Ming-Dou Ker, Guido Groeseneken

Research output: Contribution to journal › Article › peer-review

6 Scopus citations

Abstract

CDM ESD events can be a potential threat to SoC designs or heterogeneous 3D ICs with multiple power domains. Inter-layer (or interface) circuits may need a local CDM ESD clamp that can prevent the unexpected failure under CDM ESD stress. In this letter, two local CDM ESD clamp circuits are proposed. They show better clamping efficiency under 2-ns vfTLP stress.

Original language	English
Article number	6807728
Pages (from-to)	781-783
Number of pages	3
Journal	IEEE Transactions on Device and Materials Reliability
Volume	14
Issue number	2
DOIs	https://doi.org/10.1109/TDMR.2014.2320538
State	Published - 1 Jan 2014

Keywords

3D stacked ICs
charged device model (CDM)
cross-power domains ESD events
Electrostatic discharge (ESD)
vary-fast transmission line pulsing (vfTLP) systems

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10.1109/TDMR.2014.2320538

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title = "Local CDM ESD protection circuits for cross-power domains in 3D IC applications",

abstract = "CDM ESD events can be a potential threat to SoC designs or heterogeneous 3D ICs with multiple power domains. Inter-layer (or interface) circuits may need a local CDM ESD clamp that can prevent the unexpected failure under CDM ESD stress. In this letter, two local CDM ESD clamp circuits are proposed. They show better clamping efficiency under 2-ns vfTLP stress.",

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AU - Chen, Shih Hung

AU - Linten, Dimitri

AU - Scholz, Mirko

AU - Huang, Yu Ching

AU - Hellings, Geert

AU - Boschke, Roman

AU - Ker, Ming-Dou

AU - Groeseneken, Guido

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AB - CDM ESD events can be a potential threat to SoC designs or heterogeneous 3D ICs with multiple power domains. Inter-layer (or interface) circuits may need a local CDM ESD clamp that can prevent the unexpected failure under CDM ESD stress. In this letter, two local CDM ESD clamp circuits are proposed. They show better clamping efficiency under 2-ns vfTLP stress.

KW - 3D stacked ICs

KW - charged device model (CDM)

KW - cross-power domains ESD events

KW - Electrostatic discharge (ESD)

KW - vary-fast transmission line pulsing (vfTLP) systems

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Local CDM ESD protection circuits for cross-power domains in 3D IC applications

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Keywords

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