Lithography-aware 1-dimensional cell generation

Po Hsun Wu; Po-Hung Lin; Tung Chieh Chen; Tsung Yi Ho; Yu Chuan Chen

doi:10.1109/ECCTD.2013.6662310

Lithography-aware 1-dimensional cell generation

Po Hsun Wu, Po-Hung Lin, Tung Chieh Chen, Tsung Yi Ho, Yu Chuan Chen

Institute of Intelligent Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

As the process technology advances to the sub-wavelength era, the 1-dimensional (1-D) design style is regarded as one of the most effective ways to continue scaling down the minimum feature size. This paper presents the lithography-aware cell generation algorithms which simultaneously minimize 1-D cell area and enhance the printability. Experimental results show that the proposed algorithms can effectively and efficiently reduce the number of diffusion gaps, and minimize used routing tracks. Consequently, our approach results in smaller 1-D cell area and better printability.

Original language	English
Title of host publication	2013 European Conference on Circuit Theory and Design, ECCTD 2013 - Proceedings
Publisher	IEEE Computer Society
ISBN (Print)	9783000437854
DOIs	https://doi.org/10.1109/ECCTD.2013.6662310
State	Published - 2013
Event	2013 European Conference on Circuit Theory and Design, ECCTD 2013 - Dresden, Germany Duration: 8 Sep 2013 → 12 Sep 2013

Publication series

Name	2013 European Conference on Circuit Theory and Design, ECCTD 2013 - Proceedings

Conference

Conference	2013 European Conference on Circuit Theory and Design, ECCTD 2013
Country/Territory	Germany
City	Dresden
Period	8/09/13 → 12/09/13

Access to Document

10.1109/ECCTD.2013.6662310

Cite this

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title = "Lithography-aware 1-dimensional cell generation",

abstract = "As the process technology advances to the sub-wavelength era, the 1-dimensional (1-D) design style is regarded as one of the most effective ways to continue scaling down the minimum feature size. This paper presents the lithography-aware cell generation algorithms which simultaneously minimize 1-D cell area and enhance the printability. Experimental results show that the proposed algorithms can effectively and efficiently reduce the number of diffusion gaps, and minimize used routing tracks. Consequently, our approach results in smaller 1-D cell area and better printability.",

author = "Wu, {Po Hsun} and Po-Hung Lin and Chen, {Tung Chieh} and Ho, {Tsung Yi} and Chen, {Yu Chuan}",

year = "2013",

doi = "10.1109/ECCTD.2013.6662310",

language = "English",

isbn = "9783000437854",

series = "2013 European Conference on Circuit Theory and Design, ECCTD 2013 - Proceedings",

publisher = "IEEE Computer Society",

booktitle = "2013 European Conference on Circuit Theory and Design, ECCTD 2013 - Proceedings",

address = "United States",

note = "2013 European Conference on Circuit Theory and Design, ECCTD 2013 ; Conference date: 08-09-2013 Through 12-09-2013",

}

Wu, PH, Lin, P-H, Chen, TC, Ho, TY & Chen, YC 2013, Lithography-aware 1-dimensional cell generation. in 2013 European Conference on Circuit Theory and Design, ECCTD 2013 - Proceedings., 6662310, 2013 European Conference on Circuit Theory and Design, ECCTD 2013 - Proceedings, IEEE Computer Society, 2013 European Conference on Circuit Theory and Design, ECCTD 2013, Dresden, Germany, 8/09/13. https://doi.org/10.1109/ECCTD.2013.6662310

Lithography-aware 1-dimensional cell generation. / Wu, Po Hsun; Lin, Po-Hung; Chen, Tung Chieh et al.
2013 European Conference on Circuit Theory and Design, ECCTD 2013 - Proceedings. IEEE Computer Society, 2013. 6662310 (2013 European Conference on Circuit Theory and Design, ECCTD 2013 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Lithography-aware 1-dimensional cell generation

AU - Wu, Po Hsun

AU - Lin, Po-Hung

AU - Chen, Tung Chieh

AU - Ho, Tsung Yi

AU - Chen, Yu Chuan

PY - 2013

Y1 - 2013

N2 - As the process technology advances to the sub-wavelength era, the 1-dimensional (1-D) design style is regarded as one of the most effective ways to continue scaling down the minimum feature size. This paper presents the lithography-aware cell generation algorithms which simultaneously minimize 1-D cell area and enhance the printability. Experimental results show that the proposed algorithms can effectively and efficiently reduce the number of diffusion gaps, and minimize used routing tracks. Consequently, our approach results in smaller 1-D cell area and better printability.

AB - As the process technology advances to the sub-wavelength era, the 1-dimensional (1-D) design style is regarded as one of the most effective ways to continue scaling down the minimum feature size. This paper presents the lithography-aware cell generation algorithms which simultaneously minimize 1-D cell area and enhance the printability. Experimental results show that the proposed algorithms can effectively and efficiently reduce the number of diffusion gaps, and minimize used routing tracks. Consequently, our approach results in smaller 1-D cell area and better printability.

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DO - 10.1109/ECCTD.2013.6662310

M3 - Conference contribution

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SN - 9783000437854

T3 - 2013 European Conference on Circuit Theory and Design, ECCTD 2013 - Proceedings

BT - 2013 European Conference on Circuit Theory and Design, ECCTD 2013 - Proceedings

PB - IEEE Computer Society

T2 - 2013 European Conference on Circuit Theory and Design, ECCTD 2013

Y2 - 8 September 2013 through 12 September 2013

ER -

Lithography-aware 1-dimensional cell generation

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