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Linear low voltage nano-scale CMOS transconductor
Tien Yu Lo
,
Chung-Chih Hung
*
, Chi Hsiang Lo
*
Corresponding author for this work
Department of Electrical and Computer Engineering
Research output
:
Contribution to journal
›
Article
›
peer-review
7
Scopus citations
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Keyphrases
Measurement Results
100%
Nanoscale CMOS
100%
Low Voltage
100%
Transistor
100%
CMOS Transconductor
100%
CMOS Process
50%
Supply Voltage
50%
BSIM4
50%
Compensation Method
50%
High Linearity
50%
Transconductance
50%
Device Sizing
50%
Differential Input
50%
Downscaling
50%
Saturation Region
50%
Subthreshold Region
50%
Transconductor
50%
Static Power Consumption
50%
Differential Structure
50%
Transistor Model
50%
Mobility Compensation
50%
MOSFET-only
50%
Engineering
Nanoscale
100%
Supply Voltage
50%
Power Supply
50%
Metal-Oxide-Semiconductor Field-Effect Transistor
50%
Electric Power Utilization
50%
Differential Input
50%
Saturation Region
50%
Material Science
Transistor
100%
Electronic Circuit
33%
Metal-Oxide-Semiconductor Field-Effect Transistor
33%