Level shifters for high-speed 1-V to 3.3-V interfaces in a 0.13-μm Cu-interconnection/low-k CMOS technology

W. T. Wang*, Ming-Dou Ker, M. C. Chiang, C. H. Chen

*Corresponding author for this work

    Research output: Contribution to conferencePaperpeer-review

    40 Scopus citations

    Abstract

    Level shifters for 1.0-V to 3.3-V high-speed interfaces are proposed. Level-up shifter uses zero-Vt 3.3-V NMOSs as voltage clamps to protect 1.0-V NMOS switches from high voltage stress across the gate oxide. Level-down shifter uses 3.3-V NMOSs as both pull-up and pull-down devices with supply voltage of 1.0-V and gate voltage swing from 0-V to 3.3-V. The zero-Vt NMOS is a standard MOSFET device in a 0.13-μm CMOS process without adding extra mask or process step to realize it. Level-up transition from 0.9-V to 3.6-V takes only 1 ns in time, and the level-down transition has no minimum core voltage limitation. These circuits do not consume static DC power, therefore they are very suitable for low-power and high-speed interfaces in the deep sub-quarter-micron CMOS technologies.

    Original languageEnglish
    Pages307-310
    Number of pages4
    DOIs
    StatePublished - 26 Sep 2001
    Event2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings - Hsinchu, Taiwan
    Duration: 18 Apr 200120 Apr 2001

    Conference

    Conference2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings
    Country/TerritoryTaiwan
    CityHsinchu
    Period18/04/0120/04/01

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