Abstract
Reconfigurable architectures, including FPGAs, are promising solutions for managing increasing design complexity while achieving both performance and flexibility. To support reconfiguration, FPGAs use more transistors per function than fixed-logic solutions, resulting in higher leakage power consumption. Consequently, FPGAs are generally not found in mobile applications. In this work, we analyze the leakage power of a low-cost, 90nm FPGA using detailed device-level simulations. The simulation methodology accounts for design-dependent variations and provides detailed leakage power breakdowns. The analysis quantities the leakage power challenge in FPGAs, and identifies promising approaches for FPGA leakage power reduction.
Original language | English |
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Pages (from-to) | 57-60 |
Number of pages | 4 |
Journal | Proceedings of the Custom Integrated Circuits Conference |
DOIs | |
State | Published - 2003 |
Event | Proceedings of the IEEE 2003 Custom Integrated Circuits Conference - San Jose, CA, United States Duration: 21 Sep 2003 → 24 Sep 2003 |