Layout verification to improve ESD/latchup immunity of scaled-down CMOS cell libraries

Ming-Dou Ker; Sue Mei Hsiao; Jiann Horng Lin

doi:10.1109/ASIC.1997.616991

Layout verification to improve ESD/latchup immunity of scaled-down CMOS cell libraries

Ming-Dou Ker^*, Sue Mei Hsiao, Jiann Horng Lin

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Conference article › peer-review

Abstract

Layout verification has been proposed to improve the ESD (Electrostatic Discharge) and latchup immunity of scaled-down CMOS cell libraries. By using the DRC (design rules check) and ERC (electrical rules check), the ESD/latchup sensitive layout can be found. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the cells, the ESD and latchup reliability of CMOS IC's assembled by the layout-verified cell libraries can be significantly improved.

Original language	English
Article number	5774221
Pages (from-to)	125-129
Number of pages	5
Journal	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
DOIs	https://doi.org/10.1109/ASIC.1997.616991
State	Published - 1 Jan 1997
Event	Proceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit - Portland, OR, USA Duration: 7 Sep 1997 → 10 Sep 1997

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@article{9caac4eb5ef646b4b962760c03b3a6ff,

title = "Layout verification to improve ESD/latchup immunity of scaled-down CMOS cell libraries",

abstract = "Layout verification has been proposed to improve the ESD (Electrostatic Discharge) and latchup immunity of scaled-down CMOS cell libraries. By using the DRC (design rules check) and ERC (electrical rules check), the ESD/latchup sensitive layout can be found. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the cells, the ESD and latchup reliability of CMOS IC's assembled by the layout-verified cell libraries can be significantly improved.",

author = "Ming-Dou Ker and Hsiao, {Sue Mei} and Lin, {Jiann Horng}",

year = "1997",

month = jan,

day = "1",

doi = "10.1109/ASIC.1997.616991",

language = "English",

pages = "125--129",

journal = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",

issn = "1063-0988",

note = "null ; Conference date: 07-09-1997 Through 10-09-1997",

}

TY - JOUR

T1 - Layout verification to improve ESD/latchup immunity of scaled-down CMOS cell libraries

AU - Ker, Ming-Dou

AU - Hsiao, Sue Mei

AU - Lin, Jiann Horng

PY - 1997/1/1

Y1 - 1997/1/1

N2 - Layout verification has been proposed to improve the ESD (Electrostatic Discharge) and latchup immunity of scaled-down CMOS cell libraries. By using the DRC (design rules check) and ERC (electrical rules check), the ESD/latchup sensitive layout can be found. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the cells, the ESD and latchup reliability of CMOS IC's assembled by the layout-verified cell libraries can be significantly improved.

AB - Layout verification has been proposed to improve the ESD (Electrostatic Discharge) and latchup immunity of scaled-down CMOS cell libraries. By using the DRC (design rules check) and ERC (electrical rules check), the ESD/latchup sensitive layout can be found. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the cells, the ESD and latchup reliability of CMOS IC's assembled by the layout-verified cell libraries can be significantly improved.

UR - http://www.scopus.com/inward/record.url?scp=0030655535&partnerID=8YFLogxK

U2 - 10.1109/ASIC.1997.616991

DO - 10.1109/ASIC.1997.616991

M3 - Conference article

AN - SCOPUS:0030655535

SN - 1063-0988

SP - 125

EP - 129

JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

M1 - 5774221

Y2 - 7 September 1997 through 10 September 1997

ER -

Layout verification to improve ESD/latchup immunity of scaled-down CMOS cell libraries

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