Layout verification for submicron CMOS cell libraries to improve ESD/latchup reliability

Ming-Dou Ker; Sue Mei Hsiao; Jiann Horng Lin

doi:10.1109/VTSA.1997.614930

Layout verification for submicron CMOS cell libraries to improve ESD/latchup reliability

Ming-Dou Ker^*, Sue Mei Hsiao, Jiann Horng Lin

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to conference › Paper › peer-review

Abstract

Layout verification has been proposed to improve the ESD and latchup immunity of scaled-down CMOS cell libraries. By using the DRC (design rules check) and ERC (electrical rules check), the layout sensitive to the ESD or latchup events can be found. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the cells, the ESD and latchup reliability of CMOS IC's assembled by the layout-verified cell libraries can be significantly improved.

Original language	English
Pages	343-347
Number of pages	5
DOIs	https://doi.org/10.1109/VTSA.1997.614930
State	Published - 1 Jan 1997
Event	Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications - Taipei, China Duration: 3 Jun 1997 → 5 Jun 1997

Conference

Conference	Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications
City	Taipei, China
Period	3/06/97 → 5/06/97

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10.1109/VTSA.1997.614930

Cite this

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abstract = "Layout verification has been proposed to improve the ESD and latchup immunity of scaled-down CMOS cell libraries. By using the DRC (design rules check) and ERC (electrical rules check), the layout sensitive to the ESD or latchup events can be found. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the cells, the ESD and latchup reliability of CMOS IC's assembled by the layout-verified cell libraries can be significantly improved.",

author = "Ming-Dou Ker and Hsiao, {Sue Mei} and Lin, {Jiann Horng}",

year = "1997",

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doi = "10.1109/VTSA.1997.614930",

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AU - Hsiao, Sue Mei

AU - Lin, Jiann Horng

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N2 - Layout verification has been proposed to improve the ESD and latchup immunity of scaled-down CMOS cell libraries. By using the DRC (design rules check) and ERC (electrical rules check), the layout sensitive to the ESD or latchup events can be found. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the cells, the ESD and latchup reliability of CMOS IC's assembled by the layout-verified cell libraries can be significantly improved.

AB - Layout verification has been proposed to improve the ESD and latchup immunity of scaled-down CMOS cell libraries. By using the DRC (design rules check) and ERC (electrical rules check), the layout sensitive to the ESD or latchup events can be found. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the cells, the ESD and latchup reliability of CMOS IC's assembled by the layout-verified cell libraries can be significantly improved.

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M3 - Paper

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T2 - Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications

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ER -

Layout verification for submicron CMOS cell libraries to improve ESD/latchup reliability

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