Layout optimization on low-voltage-triggered PNP devices for ESD protection in mixed-voltage I/O interfaces

Wei Jen Chang; Ming-Dou Ker

doi:10.1109/IPFA.2004.1345599

Layout optimization on low-voltage-triggered PNP devices for ESD protection in mixed-voltage I/O interfaces

Wei Jen Chang^*
, Ming-Dou Ker

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

4 Scopus citations

Abstract

Layout optimization on low-voltage-triggered PNP (LVTPNP) devices for ESD protection in mixed-voltage I/O interfaces is proposed in this paper. The experimental results in both 0.35-μm and 0.25-μm CMOS processes have proven that the ESD levels of the LVTPNP drawn in the multi-finger layout style are higher than that drawn in the original layout style. Moreover, the LVTPNP device in multi-finger layout style has been implemented in a 0.25-μm salicided CMOS process to protect successfully the input stage of an ADSL IC with power-rail ESD clamp circuit.

Original language	English
Pages	213-216
Number of pages	4
DOIs	https://doi.org/10.1109/IPFA.2004.1345599
State	Published - Jul 2004
Event	Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004 - , Taiwan Duration: 5 Jul 2004 → 8 Jul 2004

Conference

Conference	Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004
Country/Territory	Taiwan
Period	5/07/04 → 8/07/04

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10.1109/IPFA.2004.1345599

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title = "Layout optimization on low-voltage-triggered PNP devices for ESD protection in mixed-voltage I/O interfaces",

abstract = "Layout optimization on low-voltage-triggered PNP (LVTPNP) devices for ESD protection in mixed-voltage I/O interfaces is proposed in this paper. The experimental results in both 0.35-μm and 0.25-μm CMOS processes have proven that the ESD levels of the LVTPNP drawn in the multi-finger layout style are higher than that drawn in the original layout style. Moreover, the LVTPNP device in multi-finger layout style has been implemented in a 0.25-μm salicided CMOS process to protect successfully the input stage of an ADSL IC with power-rail ESD clamp circuit.",

author = "Chang, \{Wei Jen\} and Ming-Dou Ker",

year = "2004",

month = jul,

doi = "10.1109/IPFA.2004.1345599",

language = "English",

pages = "213--216",

note = "Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004 ; Conference date: 05-07-2004 Through 08-07-2004",

}

Layout optimization on low-voltage-triggered PNP devices for ESD protection in mixed-voltage I/O interfaces. / Chang, Wei Jen; Ker, Ming-Dou.
2004. 213-216 Paper presented at Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004, Taiwan.

Research output: Contribution to conference › Paper › peer-review

TY - CONF

T1 - Layout optimization on low-voltage-triggered PNP devices for ESD protection in mixed-voltage I/O interfaces

AU - Chang, Wei Jen

AU - Ker, Ming-Dou

PY - 2004/7

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N2 - Layout optimization on low-voltage-triggered PNP (LVTPNP) devices for ESD protection in mixed-voltage I/O interfaces is proposed in this paper. The experimental results in both 0.35-μm and 0.25-μm CMOS processes have proven that the ESD levels of the LVTPNP drawn in the multi-finger layout style are higher than that drawn in the original layout style. Moreover, the LVTPNP device in multi-finger layout style has been implemented in a 0.25-μm salicided CMOS process to protect successfully the input stage of an ADSL IC with power-rail ESD clamp circuit.

AB - Layout optimization on low-voltage-triggered PNP (LVTPNP) devices for ESD protection in mixed-voltage I/O interfaces is proposed in this paper. The experimental results in both 0.35-μm and 0.25-μm CMOS processes have proven that the ESD levels of the LVTPNP drawn in the multi-finger layout style are higher than that drawn in the original layout style. Moreover, the LVTPNP device in multi-finger layout style has been implemented in a 0.25-μm salicided CMOS process to protect successfully the input stage of an ADSL IC with power-rail ESD clamp circuit.

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DO - 10.1109/IPFA.2004.1345599

M3 - Paper

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T2 - Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004

Y2 - 5 July 2004 through 8 July 2004

ER -

Layout optimization on low-voltage-triggered PNP devices for ESD protection in mixed-voltage I/O interfaces

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