Layout optimization on ESD diodes for giga-Hz RF and high-speed I/O circuits

Chih Ting Yeh; Yung Chih Liang; Ming-Dou Ker

doi:10.1109/VDAT.2010.5496734

Layout optimization on ESD diodes for giga-Hz RF and high-speed I/O circuits

Chih Ting Yeh^*, Yung Chih Liang, Ming-Dou Ker

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

The diode operated in forward-biased condition has been widely used as an effective on-chip ESD protection device at GHz RF and high-speed I/O pads due to the small parasitic loading effect and high ESD robustness in CMOS integrated circuits (ICs). This work presents new ESD protection diodes realized in the octagon, waffle-hollow, and octagon-hollow layout styles to improve the efficiency of ESD current distribution and to reduce the parasitic capacitance. The new ESD protection diodes can achieve smaller parasitic capacitance under the same ESD robustness level as compared to the waffle diode. Therefore, the signal degradation of GHz RF and high-speed transmission can be reduced due to smaller parasitic capacitance from the new proposed diodes.

Original language	English
Title of host publication	Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
Pages	241-244
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2010.5496734
State	Published - 8 Nov 2010
Event	2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 - Hsin Chu, Taiwan Duration: 26 Apr 2010 → 29 Apr 2010

Publication series

Name	Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010

Conference

Conference	2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010
Country/Territory	Taiwan
City	Hsin Chu
Period	26/04/10 → 29/04/10

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10.1109/VDAT.2010.5496734

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Yeh, C. T., Liang, Y. C., & Ker, M.-D. (2010). Layout optimization on ESD diodes for giga-Hz RF and high-speed I/O circuits. In Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 (pp. 241-244). Article 5496734 (Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010). https://doi.org/10.1109/VDAT.2010.5496734

@inproceedings{c3e5b8ba6a8f42d1961f3a74decc6900,

title = "Layout optimization on ESD diodes for giga-Hz RF and high-speed I/O circuits",

abstract = "The diode operated in forward-biased condition has been widely used as an effective on-chip ESD protection device at GHz RF and high-speed I/O pads due to the small parasitic loading effect and high ESD robustness in CMOS integrated circuits (ICs). This work presents new ESD protection diodes realized in the octagon, waffle-hollow, and octagon-hollow layout styles to improve the efficiency of ESD current distribution and to reduce the parasitic capacitance. The new ESD protection diodes can achieve smaller parasitic capacitance under the same ESD robustness level as compared to the waffle diode. Therefore, the signal degradation of GHz RF and high-speed transmission can be reduced due to smaller parasitic capacitance from the new proposed diodes.",

author = "Yeh, {Chih Ting} and Liang, {Yung Chih} and Ming-Dou Ker",

year = "2010",

month = nov,

day = "8",

doi = "10.1109/VDAT.2010.5496734",

language = "English",

isbn = "9781424452712",

series = "Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010",

pages = "241--244",

booktitle = "Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010",

note = "2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010 ; Conference date: 26-04-2010 Through 29-04-2010",

}

Yeh, CT, Liang, YC & Ker, M-D 2010, Layout optimization on ESD diodes for giga-Hz RF and high-speed I/O circuits. in Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010., 5496734, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010, pp. 241-244, 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010, Hsin Chu, Taiwan, 26/04/10. https://doi.org/10.1109/VDAT.2010.5496734

Layout optimization on ESD diodes for giga-Hz RF and high-speed I/O circuits. / Yeh, Chih Ting; Liang, Yung Chih; Ker, Ming-Dou.
Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010. 2010. p. 241-244 5496734 (Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Layout optimization on ESD diodes for giga-Hz RF and high-speed I/O circuits

AU - Yeh, Chih Ting

AU - Liang, Yung Chih

AU - Ker, Ming-Dou

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Y1 - 2010/11/8

N2 - The diode operated in forward-biased condition has been widely used as an effective on-chip ESD protection device at GHz RF and high-speed I/O pads due to the small parasitic loading effect and high ESD robustness in CMOS integrated circuits (ICs). This work presents new ESD protection diodes realized in the octagon, waffle-hollow, and octagon-hollow layout styles to improve the efficiency of ESD current distribution and to reduce the parasitic capacitance. The new ESD protection diodes can achieve smaller parasitic capacitance under the same ESD robustness level as compared to the waffle diode. Therefore, the signal degradation of GHz RF and high-speed transmission can be reduced due to smaller parasitic capacitance from the new proposed diodes.

AB - The diode operated in forward-biased condition has been widely used as an effective on-chip ESD protection device at GHz RF and high-speed I/O pads due to the small parasitic loading effect and high ESD robustness in CMOS integrated circuits (ICs). This work presents new ESD protection diodes realized in the octagon, waffle-hollow, and octagon-hollow layout styles to improve the efficiency of ESD current distribution and to reduce the parasitic capacitance. The new ESD protection diodes can achieve smaller parasitic capacitance under the same ESD robustness level as compared to the waffle diode. Therefore, the signal degradation of GHz RF and high-speed transmission can be reduced due to smaller parasitic capacitance from the new proposed diodes.

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SN - 9781424452712

T3 - Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010

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BT - Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010

T2 - 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010

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ER -

Layout optimization on ESD diodes for giga-Hz RF and high-speed I/O circuits

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