Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-μm salicided CMOS process

Ming-Dou Ker; Che Hao Chuang; Wen Yu Lo

doi:10.1109/ICECS.2001.957754

Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-μm salicided CMOS process

Ming-Dou Ker^*, Che Hao Chuang, Wen Yu Lo

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

18 Scopus citations

Abstract

The layout design to improve uniform ESD current distribution in multi-finger MOSFET devices for better ESD robustness is investigated in a 0.18-μm salicided CMOS process. The multi-finger MOSFET, without adding the pick-up guard ring inserted into its source region, or with the vertical direction of power line connection, can sustain a higher ESD level. The layout of I/O cell can be drawn more compactly, but still to provide deep-submicron CMOS IC's with higher ESD robustness.

Original language	English
Title of host publication	ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems
Pages	361-364
Number of pages	4
DOIs	https://doi.org/10.1109/ICECS.2001.957754
State	Published - 1 Dec 2001
Event	8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001 - , Malta Duration: 2 Sep 2001 → 5 Sep 2001

Publication series

Name	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume	1

Conference

Conference	8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001
Country/Territory	Malta
Period	2/09/01 → 5/09/01

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10.1109/ICECS.2001.957754

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Ker, M.-D., Chuang, C. H., & Lo, W. Y. (2001). Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-μm salicided CMOS process. In ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems (pp. 361-364). Article 957754 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 1). https://doi.org/10.1109/ICECS.2001.957754

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title = "Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-μm salicided CMOS process",

abstract = "The layout design to improve uniform ESD current distribution in multi-finger MOSFET devices for better ESD robustness is investigated in a 0.18-μm salicided CMOS process. The multi-finger MOSFET, without adding the pick-up guard ring inserted into its source region, or with the vertical direction of power line connection, can sustain a higher ESD level. The layout of I/O cell can be drawn more compactly, but still to provide deep-submicron CMOS IC's with higher ESD robustness.",

author = "Ming-Dou Ker and Chuang, {Che Hao} and Lo, {Wen Yu}",

year = "2001",

month = dec,

day = "1",

doi = "10.1109/ICECS.2001.957754",

language = "English",

isbn = "0780370570",

series = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",

pages = "361--364",

booktitle = "ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems",

note = "8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001 ; Conference date: 02-09-2001 Through 05-09-2001",

}

Ker, M-D, Chuang, CH & Lo, WY 2001, Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-μm salicided CMOS process. in ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems., 957754, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, vol. 1, pp. 361-364, 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, 2/09/01. https://doi.org/10.1109/ICECS.2001.957754

Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-μm salicided CMOS process. / Ker, Ming-Dou; Chuang, Che Hao; Lo, Wen Yu.
ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems. 2001. p. 361-364 957754 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Ker, Ming-Dou

AU - Chuang, Che Hao

AU - Lo, Wen Yu

PY - 2001/12/1

Y1 - 2001/12/1

N2 - The layout design to improve uniform ESD current distribution in multi-finger MOSFET devices for better ESD robustness is investigated in a 0.18-μm salicided CMOS process. The multi-finger MOSFET, without adding the pick-up guard ring inserted into its source region, or with the vertical direction of power line connection, can sustain a higher ESD level. The layout of I/O cell can be drawn more compactly, but still to provide deep-submicron CMOS IC's with higher ESD robustness.

AB - The layout design to improve uniform ESD current distribution in multi-finger MOSFET devices for better ESD robustness is investigated in a 0.18-μm salicided CMOS process. The multi-finger MOSFET, without adding the pick-up guard ring inserted into its source region, or with the vertical direction of power line connection, can sustain a higher ESD level. The layout of I/O cell can be drawn more compactly, but still to provide deep-submicron CMOS IC's with higher ESD robustness.

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DO - 10.1109/ICECS.2001.957754

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SN - 9780780370579

T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

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BT - ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems

T2 - 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001

Y2 - 2 September 2001 through 5 September 2001

ER -

Ker MD, Chuang CH, Lo WY. Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-μm salicided CMOS process. In ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems. 2001. p. 361-364. 957754. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). doi: 10.1109/ICECS.2001.957754

Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-μm salicided CMOS process

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