Layout design considerations in MOS continuous-time integrated filters

Shirley Smith; Mohammed Ismail; Chung-Chih Hung; Shu Chuan Huang

doi:10.1109/APCCAS.1994.514566

Layout design considerations in MOS continuous-time integrated filters

Shirley Smith^*, Mohammed Ismail, Chung-Chih Hung, Shu Chuan Huang

^*Corresponding author for this work

Department of Electrical and Computer Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract

Analysis of two layout designs used in the realization of MOS continuous-time integrated filters is presented. The effect of MOS parasitic capacitances is thoroughly studied and compared in the two layout design techniques. It is found that one layout method performs well at high frequencies or high Q, at the expense of increased harmonic distortion in comparison with the other method. A tradeoff between transistor matching and sensitivity to MOS intrinsic parasitic capacitances is revealed. A set of performance graphs are developed with the ratio of parasitic to integrating capacitance, C _p /C, as a parameter. These graphs are useful in the design of high performance MOS continuous-time integrated filters.

Original language	English
Pages	300-305
Number of pages	6
DOIs	https://doi.org/10.1109/APCCAS.1994.514566
State	Published - 1 Dec 1994
Event	Proceedings of the 1994 IEEE Asia-Pacific Conference on Circuits and Systems - Taipei, Taiwan Duration: 5 Dec 1994 → 8 Dec 1994

Conference

Conference	Proceedings of the 1994 IEEE Asia-Pacific Conference on Circuits and Systems
City	Taipei, Taiwan
Period	5/12/94 → 8/12/94

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10.1109/APCCAS.1994.514566

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abstract = " Analysis of two layout designs used in the realization of MOS continuous-time integrated filters is presented. The effect of MOS parasitic capacitances is thoroughly studied and compared in the two layout design techniques. It is found that one layout method performs well at high frequencies or high Q, at the expense of increased harmonic distortion in comparison with the other method. A tradeoff between transistor matching and sensitivity to MOS intrinsic parasitic capacitances is revealed. A set of performance graphs are developed with the ratio of parasitic to integrating capacitance, C p /C, as a parameter. These graphs are useful in the design of high performance MOS continuous-time integrated filters. ",

author = "Shirley Smith and Mohammed Ismail and Chung-Chih Hung and Huang, {Shu Chuan}",

year = "1994",

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doi = "10.1109/APCCAS.1994.514566",

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AU - Hung, Chung-Chih

AU - Huang, Shu Chuan

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N2 - Analysis of two layout designs used in the realization of MOS continuous-time integrated filters is presented. The effect of MOS parasitic capacitances is thoroughly studied and compared in the two layout design techniques. It is found that one layout method performs well at high frequencies or high Q, at the expense of increased harmonic distortion in comparison with the other method. A tradeoff between transistor matching and sensitivity to MOS intrinsic parasitic capacitances is revealed. A set of performance graphs are developed with the ratio of parasitic to integrating capacitance, C p /C, as a parameter. These graphs are useful in the design of high performance MOS continuous-time integrated filters.

AB - Analysis of two layout designs used in the realization of MOS continuous-time integrated filters is presented. The effect of MOS parasitic capacitances is thoroughly studied and compared in the two layout design techniques. It is found that one layout method performs well at high frequencies or high Q, at the expense of increased harmonic distortion in comparison with the other method. A tradeoff between transistor matching and sensitivity to MOS intrinsic parasitic capacitances is revealed. A set of performance graphs are developed with the ratio of parasitic to integrating capacitance, C p /C, as a parameter. These graphs are useful in the design of high performance MOS continuous-time integrated filters.

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T2 - Proceedings of the 1994 IEEE Asia-Pacific Conference on Circuits and Systems

Y2 - 5 December 1994 through 8 December 1994

ER -

Layout design considerations in MOS continuous-time integrated filters

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