Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology

Ming-Dou Ker; Jeng Jie Peng

doi:10.1109/CICC.1998.695035

Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology

Ming-Dou Ker^*, Jeng Jie Peng

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Conference article › peer-review

7 Scopus citations

Abstract

A methodology to verify the ESD and latchup reliability of CMOS cell libraries has been proposed. The ESD- or latchup-sensitive layout in the cell library can be found by this proposed methodology with DRC (design rules check) and ERC (electrical rules check), before the chip is fabricated. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the internal cores, the ESD and latchup reliability of CMOS IC's assembled by the verified cell library can be significantly improved without trial-and-error design modification and wafer fabrication.

Original language	English
Pages (from-to)	537-540
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.1998.695035
State	Published - 1 Jan 1998
Event	Proceedings of the 1998 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA Duration: 11 May 1998 → 14 May 1998

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@article{995285e0a8c347c286c80a35b6fd3746,

title = "Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology",

abstract = "A methodology to verify the ESD and latchup reliability of CMOS cell libraries has been proposed. The ESD- or latchup-sensitive layout in the cell library can be found by this proposed methodology with DRC (design rules check) and ERC (electrical rules check), before the chip is fabricated. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the internal cores, the ESD and latchup reliability of CMOS IC's assembled by the verified cell library can be significantly improved without trial-and-error design modification and wafer fabrication.",

author = "Ming-Dou Ker and Peng, {Jeng Jie}",

year = "1998",

month = jan,

day = "1",

doi = "10.1109/CICC.1998.695035",

language = "English",

pages = "537--540",

journal = "Proceedings of the Custom Integrated Circuits Conference",

issn = "0886-5930",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "null ; Conference date: 11-05-1998 Through 14-05-1998",

}

TY - JOUR

T1 - Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology

AU - Ker, Ming-Dou

AU - Peng, Jeng Jie

PY - 1998/1/1

Y1 - 1998/1/1

N2 - A methodology to verify the ESD and latchup reliability of CMOS cell libraries has been proposed. The ESD- or latchup-sensitive layout in the cell library can be found by this proposed methodology with DRC (design rules check) and ERC (electrical rules check), before the chip is fabricated. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the internal cores, the ESD and latchup reliability of CMOS IC's assembled by the verified cell library can be significantly improved without trial-and-error design modification and wafer fabrication.

AB - A methodology to verify the ESD and latchup reliability of CMOS cell libraries has been proposed. The ESD- or latchup-sensitive layout in the cell library can be found by this proposed methodology with DRC (design rules check) and ERC (electrical rules check), before the chip is fabricated. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the internal cores, the ESD and latchup reliability of CMOS IC's assembled by the verified cell library can be significantly improved without trial-and-error design modification and wafer fabrication.

UR - http://www.scopus.com/inward/record.url?scp=0031631932&partnerID=8YFLogxK

U2 - 10.1109/CICC.1998.695035

DO - 10.1109/CICC.1998.695035

M3 - Conference article

AN - SCOPUS:0031631932

SN - 0886-5930

SP - 537

EP - 540

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

Y2 - 11 May 1998 through 14 May 1998

ER -

Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology

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