TY - GEN
T1 - Layer-aware design partitioning for vertical interconnect minimization
AU - Huang, Ya Shih
AU - Liu, Yang Hsiang
AU - Huang, Juinn-Dar
PY - 2011/9/14
Y1 - 2011/9/14
N2 - Three-dimensional (3D) design technology, which has potential to significantly improve design performance and ease heterogeneous system integration, has been extensively discussed in recent years. This emerging technology allows stacking multiple layers of dies and typically resolves the vertical inter-layer connection issue by through-silicon vias (TSVs). However, TSVs also occupy significant silicon estate as well as incur reliability problems. Therefore, the deployment of TSVs must be very judicious in 3D designs. In this paper, we propose an iterative layer-aware partitioning algorithm, named iLap, for TSV minimization in 3D structures. iLap iteratively applies multi-way min-cut partitioning to gradually divide a given design layer by layer in the bottom-up fashion. Meanwhile, iLap also properly fulfills a specific I/O pad constraint incurred by 3D structures to further improve its outcome. Experimental results show that iLap can reduce the number of TSVs by about 35% as compared to several existing state-of-the-art methods. We believe a good TSV-minimized 3D partitioning solution can serve as a good starting point for further tradeoff operations between TSV count and wirelength.
AB - Three-dimensional (3D) design technology, which has potential to significantly improve design performance and ease heterogeneous system integration, has been extensively discussed in recent years. This emerging technology allows stacking multiple layers of dies and typically resolves the vertical inter-layer connection issue by through-silicon vias (TSVs). However, TSVs also occupy significant silicon estate as well as incur reliability problems. Therefore, the deployment of TSVs must be very judicious in 3D designs. In this paper, we propose an iterative layer-aware partitioning algorithm, named iLap, for TSV minimization in 3D structures. iLap iteratively applies multi-way min-cut partitioning to gradually divide a given design layer by layer in the bottom-up fashion. Meanwhile, iLap also properly fulfills a specific I/O pad constraint incurred by 3D structures to further improve its outcome. Experimental results show that iLap can reduce the number of TSVs by about 35% as compared to several existing state-of-the-art methods. We believe a good TSV-minimized 3D partitioning solution can serve as a good starting point for further tradeoff operations between TSV count and wirelength.
KW - 3D integration technology
KW - Layering
KW - Partitioning
KW - Through-silicon via (TSV)
UR - http://www.scopus.com/inward/record.url?scp=80052597638&partnerID=8YFLogxK
U2 - 10.1109/ISVLSI.2011.16
DO - 10.1109/ISVLSI.2011.16
M3 - Conference contribution
AN - SCOPUS:80052597638
SN - 9780769544472
T3 - Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011
SP - 144
EP - 149
BT - Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011
T2 - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011
Y2 - 4 July 2011 through 6 July 2011
ER -