Late Breaking Results: PVT-Sensitive Delay Fitting for High-Performance Computing

Aggressively monitoring and tracking system-on-chip (SoC) performance under process/voltage/temperature (PVT) variations is essential for high-performance computing systems. This work observes that different chips of the same SoC design may have different PVT-to-delay sensitivities, which must be carefully considered for accurate chip performance tracking. A learning-based method is then proposed to fit critical path delay for different chips with different PVT-to-delay sensitivities. Experimental results based on the fabricated chip samples of a 7nm SoC have justified the effectiveness of the proposed PVT-sensitive delay fitting method. Compared with the state-of-the-art, our method can achieve excellent performance tracking accuracy when the chip performance is dominated by different critical paths under different PVT conditions.