Latchup Risk in a 4H-SiC Process

Chao Yang Ke, Ming Dou Ker

Research output: Contribution to journalArticlepeer-review

Abstract

This is the first study related to the latchup issue in the SiC process. In this work, the latchup risk and the holding voltage of the parasitic latchup path have been investigated. The dc holding voltage of the parasitic latchup is only 14.9 V, which is below the voltage rating (20 V) of the devices. The holding voltage measured by the transmission line pulse (TLP) system decreases when the pulsewidth increases, which can be attributed to the self-heating effect on the device. Moreover, the holding voltage measured by TLP decreases as the temperature increases. The methods to prevent latchup events are summarized in this brief. The methods can be divided into two parts. One is the process solution, and the other is the layout solution. Therefore, the design rules for latchup prevention in the SiC process must be developed.

Original languageEnglish
Pages (from-to)1-5
Number of pages5
JournalIEEE Transactions on Electron Devices
DOIs
StateAccepted/In press - 2024

Keywords

  • Electric breakdown
  • Holding voltage
  • Integrated circuits
  • latchup
  • Pulse measurements
  • SiC
  • SiC-based integrated circuits (ICs)
  • Silicon carbide
  • Temperature measurement
  • Transmission line measurements
  • Voltage measurement

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