Latchup in bulk FinFET technology

C. T. Dai, S. H. Chen, D. Linten, M. Scholz, G. Hellings, R. Boschke, J. Karp, M. Hart, G. Groeseneken, Ming-Dou Ker, A. Mocuta, N. Horiguchi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

14 Scopus citations


Latchup (LU) had been considered to be less important in advanced CMOS technologies. However, I/O interface and analog applications can still operate at high voltage (e.g., 1.8V or 3.3V) in sub-20nm bulk FinFET technologies. LU threats are never eliminated and the sensitivity towards LU is increased in bulk FinFET technology.

Original languageEnglish
Title of host publication2017 International Reliability Physics Symposium, IRPS 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509066407
StatePublished - 30 May 2017
Event2017 International Reliability Physics Symposium, IRPS 2017 - Monterey, United States
Duration: 2 Apr 20176 Apr 2017

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
ISSN (Print)1541-7026


Conference2017 International Reliability Physics Symposium, IRPS 2017
Country/TerritoryUnited States


  • Latchup
  • bulk FinFET
  • silicon control rectifier (SCR)


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