Latch-up Risk in 5V-tolerant I/O Buffer Surrounded by NBL Isolation Ring with Low-Voltage Bias

Chen Wei Hsu, Ming Dou Ker

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

For safe application of IC products, ensuring the integrity of CMOS integrated circuits (ICs) necessitates the verification of I/O pins through latch-up I-test that conforming to the standard of JEDEC JESD78F. The integration of high-voltage (HV) and low-voltage (LV) circuits within a single chip has been achieved in BCD technology. Typically, the LV circuits must be surrounded by an N-type buried layer (NBL) isolation ring to mitigate noise interference from the common p-substrate. However, in a mixed-voltage IC utilizing in 0.18-μm BCD technology, an unexpected parasitic latch-up path emerges from the 5V-tolerant I/O circuits to the NBL isolation ring. Such an unexpected parasitic latch-up path would fail the IC products to pass the requested latch-up I-test. Identifying such a latch-up risk has been practically verified in this study.

Original languageEnglish
Title of host publication2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350360349
DOIs
StatePublished - 2024
Event2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Hsinchu, Taiwan
Duration: 22 Apr 202425 Apr 2024

Publication series

Name2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Proceedings

Conference

Conference2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024
Country/TerritoryTaiwan
CityHsinchu
Period22/04/2425/04/24

Keywords

  • 5V-tolerant I/O buffer
  • BCD technology
  • Latch-up
  • N-type buried layer (NBL)
  • NBL isolation ring
  • silicon-controlled-rectifier (SCR)

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