Junctionless Poly-Si Nanowire Transistors with Low-Temperature Trimming Process for Monolithic 3-D IC Application

Jer Yi Lin; Po Yi Kuo; Ko Li Lin; Chun Chieh Chin; Tien-Sheng Chao

doi:10.1109/TED.2016.2615805

Junctionless Poly-Si Nanowire Transistors with Low-Temperature Trimming Process for Monolithic 3-D IC Application

Jer Yi Lin, Po Yi Kuo^*, Ko Li Lin, Chun Chieh Chin, Tien-Sheng Chao

^*Corresponding author for this work

Department of Electrophysics

Research output: Contribution to journal › Article › peer-review

18 Scopus citations

Abstract

In this paper, the junctionless (JL) ultrathin polycrystalline-Si (poly-Si) nanowire (NW) transistors with gate-all-around configuration and raised source/drain were successfully fabricated by a low-temperature trimming process. The 140 °C-heated phosphoric acid (HPA) was adopted for trimming the channel dimension, which exhibits a near roughness degradation-free etching and excellent trimming uniformity. As the HPA immersing time increased, the channel dimension was thinned and narrowed, resulting in the greater electrostatic integrity. Therefore, the steep subthreshold swing 75 mV/decade, low drain-induced barrier lowering ∼33 mV/V, and high on/off currents ratio (I_ON/I_OFF) ∼ 7 × 10⁶ can be achieved. These superior characteristics of low-temperature JL poly-Si NW transistors are promising candidates for the low thermal budget monolithic 3-D ICs and the system on panel applications in the future.

Original language	English
Article number	7676340
Pages (from-to)	4998-5003
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	63
Issue number	12
DOIs	https://doi.org/10.1109/TED.2016.2615805
State	Published - Dec 2016

Keywords

3-D ICs
gate-all-around (GAA)
junctionless (JL)
nanowire (NW)
polycrystalline-Si (poly-Si) thin-film transistors

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title = "Junctionless Poly-Si Nanowire Transistors with Low-Temperature Trimming Process for Monolithic 3-D IC Application",

abstract = "In this paper, the junctionless (JL) ultrathin polycrystalline-Si (poly-Si) nanowire (NW) transistors with gate-all-around configuration and raised source/drain were successfully fabricated by a low-temperature trimming process. The 140 °C-heated phosphoric acid (HPA) was adopted for trimming the channel dimension, which exhibits a near roughness degradation-free etching and excellent trimming uniformity. As the HPA immersing time increased, the channel dimension was thinned and narrowed, resulting in the greater electrostatic integrity. Therefore, the steep subthreshold swing 75 mV/decade, low drain-induced barrier lowering ∼33 mV/V, and high on/off currents ratio (ION/IOFF) ∼ 7 × 106 can be achieved. These superior characteristics of low-temperature JL poly-Si NW transistors are promising candidates for the low thermal budget monolithic 3-D ICs and the system on panel applications in the future.",

keywords = "3-D ICs, gate-all-around (GAA), junctionless (JL), nanowire (NW), polycrystalline-Si (poly-Si) thin-film transistors",

author = "Lin, {Jer Yi} and Kuo, {Po Yi} and Lin, {Ko Li} and Chin, {Chun Chieh} and Tien-Sheng Chao",

note = "Publisher Copyright: {\textcopyright} 1963-2012 IEEE.",

year = "2016",

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doi = "10.1109/TED.2016.2615805",

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AU - Lin, Jer Yi

AU - Kuo, Po Yi

AU - Lin, Ko Li

AU - Chin, Chun Chieh

AU - Chao, Tien-Sheng

PY - 2016/12

Y1 - 2016/12

N2 - In this paper, the junctionless (JL) ultrathin polycrystalline-Si (poly-Si) nanowire (NW) transistors with gate-all-around configuration and raised source/drain were successfully fabricated by a low-temperature trimming process. The 140 °C-heated phosphoric acid (HPA) was adopted for trimming the channel dimension, which exhibits a near roughness degradation-free etching and excellent trimming uniformity. As the HPA immersing time increased, the channel dimension was thinned and narrowed, resulting in the greater electrostatic integrity. Therefore, the steep subthreshold swing 75 mV/decade, low drain-induced barrier lowering ∼33 mV/V, and high on/off currents ratio (ION/IOFF) ∼ 7 × 106 can be achieved. These superior characteristics of low-temperature JL poly-Si NW transistors are promising candidates for the low thermal budget monolithic 3-D ICs and the system on panel applications in the future.

AB - In this paper, the junctionless (JL) ultrathin polycrystalline-Si (poly-Si) nanowire (NW) transistors with gate-all-around configuration and raised source/drain were successfully fabricated by a low-temperature trimming process. The 140 °C-heated phosphoric acid (HPA) was adopted for trimming the channel dimension, which exhibits a near roughness degradation-free etching and excellent trimming uniformity. As the HPA immersing time increased, the channel dimension was thinned and narrowed, resulting in the greater electrostatic integrity. Therefore, the steep subthreshold swing 75 mV/decade, low drain-induced barrier lowering ∼33 mV/V, and high on/off currents ratio (ION/IOFF) ∼ 7 × 106 can be achieved. These superior characteristics of low-temperature JL poly-Si NW transistors are promising candidates for the low thermal budget monolithic 3-D ICs and the system on panel applications in the future.

KW - 3-D ICs

KW - gate-all-around (GAA)

KW - junctionless (JL)

KW - nanowire (NW)

KW - polycrystalline-Si (poly-Si) thin-film transistors

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ER -

Junctionless Poly-Si Nanowire Transistors with Low-Temperature Trimming Process for Monolithic 3-D IC Application

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Keywords

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