Joint Management of CPU and NVDIMM for Breaking down the Great Memory Wall

Chun Feng Wu, Yuan Hao Chang*, Ming Chang Yang, Tei Wei Kuo

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

16 Scopus citations


To provide larger memory space with lower costs, NVDIMM is a production-ready device. However, directly placing NVDIMM as the main memory would seriously degrade the system performance because of the 'great memory wall' caused by the fact that in NVDIMM, the slow memory (e.g., flash memory) is several orders of magnitude slower than the fast memory (e.g., DRAM). In this article, we present a joint management framework of host/CPU and NVDIMM to break down the great memory wall by bridging the process information gap between host/CPU and NVDIMM. In this framework, a page semantic-aware strategy is proposed to precisely predict, mark, and relocate data or memory pages to the fast memory in advance by exploiting the process access patterns, so that the frequency of the slow memory accesses can be further reduced. The proposed framework with the proposed strategy was evaluated with several well-known benchmarks and the results are encouraging.

Original languageEnglish
Article number8950228
Pages (from-to)722-733
Number of pages12
JournalIEEE Transactions on Computers
Issue number5
StatePublished - 1 May 2020


  • Deep learning
  • high performance computing (HPC)
  • hybrid memory
  • large memory capacity
  • memory wall
  • process access behaviors
  • process state diagram
  • response time


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