Jitter compensation technique for continuous-time sigma-delta modulator

Zong Yi Chen; Chung-Chih Hung

doi:10.1109/APCCAS.2014.7032809

Jitter compensation technique for continuous-time sigma-delta modulator

Zong Yi Chen, Chung-Chih Hung

Department of Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

This paper proposes a new compensation technique to reduce the clock jitter effects for the continuous-time sigma-delta (CT-ΣΔ) modulator by using divided-by-n (D-N) feedback DAC waveform. There are two types of clock jitter: independent clock jitter (random jitter) and accumulated clock jitter (deterministic jitter). This technique provides a useful approach to solve one of the critical non-idealities, independent clock jitter, in the CT-ΣΔ modulator without increasing the speed requirement of the modulator as well as the complexity of system and circuit design. This technique can be implemented with the proposed DLL-based clock generator. The results prove the effectiveness of this new compensation technique for independent clock jitter.

Original language	English
Title of host publication	2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	423-426
Number of pages	4
Edition	February
ISBN (Electronic)	9781479952304
DOIs	https://doi.org/10.1109/APCCAS.2014.7032809
State	Published - 5 Feb 2015
Event	2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014 - Ishigaki Island, Okinawa, Japan Duration: 17 Nov 2014 → 20 Nov 2014

Publication series

Name	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
Number	February
Volume	2015-February

Conference

Conference	2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
Country/Territory	Japan
City	Ishigaki Island, Okinawa
Period	17/11/14 → 20/11/14

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10.1109/APCCAS.2014.7032809

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Chen, Z. Y., & Hung, C.-C. (2015). Jitter compensation technique for continuous-time sigma-delta modulator. In 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014 (February ed., pp. 423-426). Article 7032809 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; Vol. 2015-February, No. February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2014.7032809

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title = "Jitter compensation technique for continuous-time sigma-delta modulator",

abstract = "This paper proposes a new compensation technique to reduce the clock jitter effects for the continuous-time sigma-delta (CT-ΣΔ) modulator by using divided-by-n (D-N) feedback DAC waveform. There are two types of clock jitter: independent clock jitter (random jitter) and accumulated clock jitter (deterministic jitter). This technique provides a useful approach to solve one of the critical non-idealities, independent clock jitter, in the CT-ΣΔ modulator without increasing the speed requirement of the modulator as well as the complexity of system and circuit design. This technique can be implemented with the proposed DLL-based clock generator. The results prove the effectiveness of this new compensation technique for independent clock jitter.",

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Chen, ZY & Hung, C-C 2015, Jitter compensation technique for continuous-time sigma-delta modulator. in 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February edn, 7032809, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, no. February, vol. 2015-February, Institute of Electrical and Electronics Engineers Inc., pp. 423-426, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014, Ishigaki Island, Okinawa, Japan, 17/11/14. https://doi.org/10.1109/APCCAS.2014.7032809

Jitter compensation technique for continuous-time sigma-delta modulator. / Chen, Zong Yi; Hung, Chung-Chih.
2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February. ed. Institute of Electrical and Electronics Engineers Inc., 2015. p. 423-426 7032809 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; Vol. 2015-February, No. February).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Hung, Chung-Chih

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N2 - This paper proposes a new compensation technique to reduce the clock jitter effects for the continuous-time sigma-delta (CT-ΣΔ) modulator by using divided-by-n (D-N) feedback DAC waveform. There are two types of clock jitter: independent clock jitter (random jitter) and accumulated clock jitter (deterministic jitter). This technique provides a useful approach to solve one of the critical non-idealities, independent clock jitter, in the CT-ΣΔ modulator without increasing the speed requirement of the modulator as well as the complexity of system and circuit design. This technique can be implemented with the proposed DLL-based clock generator. The results prove the effectiveness of this new compensation technique for independent clock jitter.

AB - This paper proposes a new compensation technique to reduce the clock jitter effects for the continuous-time sigma-delta (CT-ΣΔ) modulator by using divided-by-n (D-N) feedback DAC waveform. There are two types of clock jitter: independent clock jitter (random jitter) and accumulated clock jitter (deterministic jitter). This technique provides a useful approach to solve one of the critical non-idealities, independent clock jitter, in the CT-ΣΔ modulator without increasing the speed requirement of the modulator as well as the complexity of system and circuit design. This technique can be implemented with the proposed DLL-based clock generator. The results prove the effectiveness of this new compensation technique for independent clock jitter.

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BT - 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014

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Chen ZY, Hung CC. Jitter compensation technique for continuous-time sigma-delta modulator. In 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February ed. Institute of Electrical and Electronics Engineers Inc. 2015. p. 423-426. 7032809. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; February). doi: 10.1109/APCCAS.2014.7032809

Jitter compensation technique for continuous-time sigma-delta modulator

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