Investigation on safe operating area and ESD robustness in a 60-V BCD process with different deep P-Well test structures

Chia Tsen Dai, Ming-Dou Ker

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    7 Scopus citations

    Abstract

    Safe operating area (SOA) is one of the noticeable reliability concerns for power MOSFETs during the normal circuit operating conditions. Besides, electrostatic discharge (ESD) reliability is another important reliability issue for the power IC products. To save the silicon area of power IC with high-voltage (HV) devices, it is preferable for HV MOSFET to be self-protected without any additional ESD protection device, and to behave wide SOA region. In this work, the impact of deep P-Well (DPW) structure to the electrical SOA (eSOA) and ESD robustness of HV MOSFET has been investigated in a 0.25-μm 60-V BCD process. DPW structure is used to implement the RESURF (reduced surface field) in MOSFET, which make it be able to sustain the high operating voltage. From the experimental results in silicon chip, the ESD robustness and eSOA of HV MOSFET can be improved by the modified DPW structure.

    Original languageEnglish
    Title of host publication2013 IEEE International Conference on Microelectronic Test Structures, ICMTS 2013 - Conference Proceedings
    Pages127-130
    Number of pages4
    DOIs
    StatePublished - 9 Aug 2013
    Event2013 International Conference on Microelectronic Test Structures, ICMTS 2013 - Osaka, Japan
    Duration: 25 Mar 201328 Mar 2013

    Publication series

    NameIEEE International Conference on Microelectronic Test Structures

    Conference

    Conference2013 International Conference on Microelectronic Test Structures, ICMTS 2013
    Country/TerritoryJapan
    CityOsaka
    Period25/03/1328/03/13

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