@inproceedings{bdef0d0fdf264f638e4790dd6fb16054,
title = "Investigation on Latch-Up Path between I/O PMOS and Core PMOS in a 0.18-μm CMOS Process",
abstract = "This work studied the latch-up path between two PMOS devices powered by different supply voltages in a 0.18μm CMOS process. In IC field applications, such a non-typical latchup path between two PMOS devices was ever fired to cause unrecoverable failures. Through the silicon test chip, the latch-up path between I/O PMOS and core PMOS was investigated in details. The measurement results from the silicon chip with split test structures can be used to investigate the design rules on anode-to-cathode spacing and guard ring placement to prevent such PMOS-to-PMOS latch-up issue. In chip layout of IC products, the PMOS devices in different power domains shall be carefully checked to prevent the occurrence of such unexpected latch-up path.",
keywords = "Design rule, Guard ring, Holding voltage, Latch-up",
author = "Chen, {Chun Cheng} and Ming-Dou Ker",
year = "2019",
month = apr,
day = "1",
doi = "10.1109/IRPS.2019.8720563",
language = "English",
series = "IEEE International Reliability Physics Symposium Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2019 IEEE International Reliability Physics Symposium, IRPS 2019",
address = "United States",
note = "null ; Conference date: 31-03-2019 Through 04-04-2019",
}