Investigation on ESD robustness of CMOS devices in a 1.8-V 0.15-μm partially-depleted SOI salicide CMOS technology

Ming-Dou Ker*, K. K. Hong, T. Y. Chen, H. Tang, S. C. Huang, S. S. Chen, C. T. Huang, M. C. Wang, Y. T. Loh

*Corresponding author for this work

    Research output: Contribution to conference › Paper › peer-review

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    Engineering

    Material Science

    Physics