Investigation on ESD robustness of CMOS devices in a 1.8-V 0.15-μm partially-depleted SOI salicide CMOS technology

Ming-Dou Ker; K. K. Hong; T. Y. Chen; H. Tang; S. C. Huang; S. S. Chen; C. T. Huang; M. C. Wang; Y. T. Loh

doi:10.1109/VTSA.2001.934478

Investigation on ESD robustness of CMOS devices in a 1.8-V 0.15-μm partially-depleted SOI salicide CMOS technology

Ming-Dou Ker^*, K. K. Hong, T. Y. Chen, H. Tang, S. C. Huang, S. S. Chen, C. T. Huang, M. C. Wang, Y. T. Loh

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

1 Scopus citations

Abstract

Electrostatic discharge (ESD) robustness of CMOS devices with four different layout structures fabricated in a 0.15-μm partially-depleted silicon-on-insulator (SOI) salicide CMOS process are verified by ESD tester. The second breakdown current (It2) of fabricated CMOS devices is also measured by the transmission line pulse generator (TLPG). The dependences of ESD robustness on the layout parameters of CMOS devices in this SOI CMOS process have been investigated to find the optimum layout rules for on-chip ESD protection design. The effectiveness of ESD clamp circuits designed with the gate-driven and substrate-triggered techniques are also compared in this SOI CMOS process.

Original language	English
Pages	41-44
Number of pages	4
DOIs	https://doi.org/10.1109/VTSA.2001.934478
State	Published - 18 Apr 2001
Event	2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings - Hsinchu, Taiwan Duration: 18 Apr 2001 → 20 Apr 2001

Conference

Conference	2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings
Country/Territory	Taiwan
City	Hsinchu
Period	18/04/01 → 20/04/01

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Ker, M-D., Hong, K. K., Chen, T. Y., Tang, H., Huang, S. C., Chen, S. S., Huang, C. T., Wang, M. C., & Loh, Y. T. (2001). Investigation on ESD robustness of CMOS devices in a 1.8-V 0.15-μm partially-depleted SOI salicide CMOS technology. 41-44. Paper presented at 2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings, Hsinchu, Taiwan. https://doi.org/10.1109/VTSA.2001.934478

@conference{ce9d50ce2d3c47c4b59097792426820f,

title = "Investigation on ESD robustness of CMOS devices in a 1.8-V 0.15-μm partially-depleted SOI salicide CMOS technology",

abstract = "Electrostatic discharge (ESD) robustness of CMOS devices with four different layout structures fabricated in a 0.15-μm partially-depleted silicon-on-insulator (SOI) salicide CMOS process are verified by ESD tester. The second breakdown current (It2) of fabricated CMOS devices is also measured by the transmission line pulse generator (TLPG). The dependences of ESD robustness on the layout parameters of CMOS devices in this SOI CMOS process have been investigated to find the optimum layout rules for on-chip ESD protection design. The effectiveness of ESD clamp circuits designed with the gate-driven and substrate-triggered techniques are also compared in this SOI CMOS process.",

author = "Ming-Dou Ker and Hong, {K. K.} and Chen, {T. Y.} and H. Tang and Huang, {S. C.} and Chen, {S. S.} and Huang, {C. T.} and Wang, {M. C.} and Loh, {Y. T.}",

year = "2001",

month = apr,

day = "18",

doi = "10.1109/VTSA.2001.934478",

language = "English",

pages = "41--44",

note = "2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings ; Conference date: 18-04-2001 Through 20-04-2001",

}

Ker, M-D, Hong, KK, Chen, TY, Tang, H, Huang, SC, Chen, SS, Huang, CT, Wang, MC & Loh, YT 2001, 'Investigation on ESD robustness of CMOS devices in a 1.8-V 0.15-μm partially-depleted SOI salicide CMOS technology', Paper presented at 2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings, Hsinchu, Taiwan, 18/04/01 - 20/04/01 pp. 41-44. https://doi.org/10.1109/VTSA.2001.934478

Investigation on ESD robustness of CMOS devices in a 1.8-V 0.15-μm partially-depleted SOI salicide CMOS technology. / Ker, Ming-Dou; Hong, K. K.; Chen, T. Y. et al.
2001. 41-44 Paper presented at 2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings, Hsinchu, Taiwan.

Research output: Contribution to conference › Paper › peer-review

TY - CONF

T1 - Investigation on ESD robustness of CMOS devices in a 1.8-V 0.15-μm partially-depleted SOI salicide CMOS technology

AU - Ker, Ming-Dou

AU - Hong, K. K.

AU - Chen, T. Y.

AU - Tang, H.

AU - Huang, S. C.

AU - Chen, S. S.

AU - Huang, C. T.

AU - Wang, M. C.

AU - Loh, Y. T.

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N2 - Electrostatic discharge (ESD) robustness of CMOS devices with four different layout structures fabricated in a 0.15-μm partially-depleted silicon-on-insulator (SOI) salicide CMOS process are verified by ESD tester. The second breakdown current (It2) of fabricated CMOS devices is also measured by the transmission line pulse generator (TLPG). The dependences of ESD robustness on the layout parameters of CMOS devices in this SOI CMOS process have been investigated to find the optimum layout rules for on-chip ESD protection design. The effectiveness of ESD clamp circuits designed with the gate-driven and substrate-triggered techniques are also compared in this SOI CMOS process.

AB - Electrostatic discharge (ESD) robustness of CMOS devices with four different layout structures fabricated in a 0.15-μm partially-depleted silicon-on-insulator (SOI) salicide CMOS process are verified by ESD tester. The second breakdown current (It2) of fabricated CMOS devices is also measured by the transmission line pulse generator (TLPG). The dependences of ESD robustness on the layout parameters of CMOS devices in this SOI CMOS process have been investigated to find the optimum layout rules for on-chip ESD protection design. The effectiveness of ESD clamp circuits designed with the gate-driven and substrate-triggered techniques are also compared in this SOI CMOS process.

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M3 - Paper

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T2 - 2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Y2 - 18 April 2001 through 20 April 2001

ER -

Investigation on ESD robustness of CMOS devices in a 1.8-V 0.15-μm partially-depleted SOI salicide CMOS technology

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