Investigation on ESD Robustness of 20-V GGNMOS and GDPMOS in 4H-SiC Process with 100-ns TLP Pulse

Chao Yang Ke*, Ming Dou Ker

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The ESD robustness of 20-V GGNMOS and GDPMOS fabricated by the 4H-SiC process was investigated by the 100-ns transmission-line-pulse (TLP) pulse. The experimental results show that, under the test of breakdown mode, there is no correlation between the ESD robustness and the number of fingers. However, under the test of forward mode, the ESD robustness can be enhanced effectively by increasing the number of fingers. When the ESD current is conducted in the forward mode through the body diode of GGNMOS or GDPMOS, the ESD robustness can be effectively enhanced. Hence, the concept and schematic diagram of the whole-chip ESD protection are proposed to achieve sufficient ESD robustness of SiC ICs. Furthermore, the power-rail ESD clamp is an indispensable element to achieve sufficient ESD robustness.

Original languageEnglish
Title of host publication2023 IEEE 10th Workshop on Wide Bandgap Power Devices and Applications, WiPDA 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350337136
DOIs
StatePublished - 2023
Event10th IEEE Workshop on Wide Bandgap Power Devices and Applications, WiPDA 2023 - Charlotte, United States
Duration: 4 Dec 20236 Dec 2023

Publication series

Name2023 IEEE 10th Workshop on Wide Bandgap Power Devices and Applications, WiPDA 2023

Conference

Conference10th IEEE Workshop on Wide Bandgap Power Devices and Applications, WiPDA 2023
Country/TerritoryUnited States
CityCharlotte
Period4/12/236/12/23

Keywords

  • body diode
  • ESD
  • GDPMOS
  • GGNMOS
  • SiC
  • TLP

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