Investigation of Vth Distribution Tails of Ground-Select-Line Cells and Edge Dummy Cells in a 3-D NAND Flash Memory

The threshold voltage ( {V} th) distributions of ground-select-line (GSL) cells and edge dummy (DMY0) cells in a 3-D NAND flash memory are investigated. We characterize the {V} th distributions in 3-D NAND flash samples with different fabrication processes and bitline voltages. Large DMY0 and GSL {V} th distribution tails are observed in certain fabrication process and operation voltage conditions. The DMY0 {V} th tail is attributed to a random distribution of grain boundary (GB) traps in a poly-silicon channel between GSL and DMY0. The GSL {V} th tail is affected by ion implant energy in an epitaxial silicon layer underneath a GSL. A 3-D TCAD simulation is performed to study the effects of a GB trap position and a bitline voltage on the {V} th distribution of DMY0. The influence of an implant dose profile in the epitaxial silicon on the GSL {V} th distribution is also analyzed by 3-D simulation. The GSL and the DMY0 {V} th distributions can be significantly improved by optimizing a fabrication process and choosing an appropriate bitline voltage.