Investigation of the time dependent gate dielectric stability in SiC MOSFETs with planar and trench gate structures

Wei Cheng Lin, Wei Chen Yu, Bang Ren Chen, Yu Sheng Hsiao, Zhen Hong Huang, Chia Lung Hung, Yi Kai Hsiao, Nai Jen Yeh, Hao Chung Kuo, Chang Ching Tu*, Tian Li Wu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

In this work, the time-dependent dielectric breakdown (TDDB) analysis is performed to understand the gate oxide reliability in SiC MOSFETs with two different structures, i.e., planar and trench gate structures. We have discovered different gate leakage current behaviors between the SiC MOSFETs with planar gate (Sample A) and trench gate (Sample B) during the forward gate bias stress. Notably, the slight increase of the gate current during the stress and the negative activation energy (Ea = −0.07 eV) observed in Sample A suggest that the hole generation caused by the impact ionization can be occurred during the forward gate TDDB tests. Furthermore, the SiC MOSFETs with trench gate structure (Sample B) exhibit the operation voltage of 55.7 V (exponential law) and 57.3 V (power law) for the 0.001 % failure of 30 years under 175 °C, indicating that SiC trench gate MOSFETs with enough thick gate dielectric (87.1 nm (bottom) and 77.9 nm (sidewall)) can have the promising forward gate TDDB stability.

Original languageEnglish
Article number115141
JournalMicroelectronics Reliability
Volume150
DOIs
StatePublished - Nov 2023

Keywords

  • MOSFETs
  • Planar
  • SiC
  • TDDB
  • Trench

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