Investigation of gate oxide short in FinFETs and the test methods for FinFET SRAMs

Chen Wei Lin, Chia-Tso Chao, Chih Chieh Hsu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

11 Scopus citations


When CMOS technologies enter nanometer scale, FinFET has become one of the most promising devices because of the superior electrical characteristics. Nonetheless, due to the scaling of dielectric thickness and the occurring of line-edge roughness, FinFETs may suffer the gate oxide short. Gate oxide short is a defect that has been widely discussed in planar bulk MOSFETs. But for FinFETs, the defect characteristics have not been studied yet. In this paper, we investigate the fault behaviors of the gate oxide short in FinFETs. The investigation includes both tied-gate and independent-gate FinFETs. Based on the TCAD mixed-mode simulations, we discover that the gate oxide short in the two types of FinFETs causes different fault behaviors from each other. Compared to planar bulk MOSFETs, the fault behaviors are even more complex. In addition to the discussion at device level, we also discuss the corresponding SRAM testing. For detecting gate oxide short in FinFET SRAMs, we propose two new test methods. By using TCAD transient simulations, we prove the two methods' test efficacy of detecting the gate oxide shorts uncovered by traditional test methods.

Original languageEnglish
Title of host publicationProceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013
StatePublished - 14 Aug 2013
Event2013 IEEE 31st VLSI Test Symposium, VTS 2013 - Berkeley, CA, United States
Duration: 29 Apr 20131 May 2013

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Conference2013 IEEE 31st VLSI Test Symposium, VTS 2013
Country/TerritoryUnited States
CityBerkeley, CA


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