Investigation of CDM ESD Protection Capability Among Power-Rail ESD Clamp Circuits in CMOS ICs with Decoupling Capacitors

Yi Chun Huang, Ming Dou Ker

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

The power-rail electrostatic discharge (ESD) clamp circuits have been widely used in CMOS integrated circuits (ICs) to provide effective discharging paths for on-chip ESD protection design. Among all ESD events, the most serious threat is posed to ICs by the charged-device model (CDM), as compared with other ESD models. In this work, the CDM ESD protection capability among different power-rail ESD clamp circuits was studied and analyzed with the very-fast transmission line pulse (VF-TLP) and all the measurements are performed at room temperature. The combinations of power-rail ESD clamp circuits with internal circuits together, which are realized by ring oscillator and different decoupling capacitors, were fabricated in the 0.18-lm CMOS technology with the 1.8-V devices to further investigate their overall CDM ESD robustness under chip-level field-induced CDM (FI-CDM) ESD stress. The investigation result of this work is helpful to provide the best selection on the power-rail ESD clamp circuit for on-chip CDM protection design in CMOS ICs.

Original languageEnglish
Pages (from-to)1
Number of pages1
JournalIEEE Journal of the Electron Devices Society
DOIs
StateAccepted/In press - 2022

Keywords

  • charged-device model (CDM)
  • Clamps
  • decoupling capacitor
  • electrostatic discharge (ESD)
  • Electrostatic discharges
  • Length measurement
  • Logic gates
  • MOS devices
  • power-rail ESD clamp circuit
  • Resistance
  • Simulation
  • very-fast transmission line pulse (VF-TLP)

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