Investigation and design of on-chip power-rail ESD clamp circuits without suffering latchup-like failure during system-level ESD test

Ming-Dou Ker*, Cheng Cheng Yen

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    56 Scopus citations

    Abstract

    On-chip power-rail electrostatic discharge (ESD) protection circuit designed with active ESD detection function is the key role to significantly improve ESD robustness of CMOS integrated circuits (ICs). Four power-rail ESD clamp circuits with different ESD-transient detection circuits were fabricated in a 0.18-μm CMOS process and tested to compare their system-level ESD susceptibility, which are named as power-rail ESD clamp circuits with typical RC-based detection, PMOS feedback, NMOS+PMOS feedback, and cascaded PMOS feedback in this work. During the system-level ESD test, where the ICs in a system have been powered up, the feedback loop used in the power-rail ESD clamp circuits provides the lock function to keep the ESD-clamping NMOS in a "latch-on" state. The latch-on ESD-damping NMOS, which is often drawn with a larger device dimension to sustain high ESD level, conducts a huge current between the power lines to perform a latchup-like failure after the system-level ESD test. A modified power-rail ESD clamp circuit is proposed to solve this problem. The proposed power-rail ESD clamp circuit can provide high enough chip-level ESD robustness, and without suffering the latchup-like failure during the system-level ESD test.

    Original languageEnglish
    Article number4685429
    Pages (from-to)2533-2545
    Number of pages13
    JournalIEEE Journal of Solid-State Circuits
    Volume43
    Issue number11
    DOIs
    StatePublished - 1 Nov 2008

    Keywords

    • Electromagnetic compatibility (EMC)
    • Electrostatic discharge (ESD)
    • ESD protection circuit
    • Latchup
    • System-level ESD test

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