Investigation and comparison of design space for ultra-thin-body GeOI/SOI negative capacitance FETs

Ho Pei Lee; Chien Lin Yu; Wei Xiang You; Pin Su

doi:10.1109/VLSI-TSA.2017.7942460

Investigation and comparison of design space for ultra-thin-body GeOI/SOI negative capacitance FETs

Ho Pei Lee, Chien Lin Yu, Wei Xiang You, Pin Su

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

Using the concept of design space, we have investigated and compared the subthreshold characteristics of UTB NCFETs with Ge/Si channel. Our results indicate that high permittivity channel is more suitable for NCFET design because of the high C_ch. Furthermore, as channel length shrinks, the optimal SS of the NCFET becomes smaller due to the drain coupling (C_DIBL). In other words, GeOI NCFETs can achieve lower SS than the Si counterpart due to their higher C_ch and C_DIBL.

Original language	English
Title of host publication	2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509058051
DOIs	https://doi.org/10.1109/VLSI-TSA.2017.7942460
State	Published - 7 Jun 2017
Event	2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017 - Hsinchu, Taiwan Duration: 24 Apr 2017 → 27 Apr 2017

Publication series

Name	2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017

Conference

Conference	2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
Country/Territory	Taiwan
City	Hsinchu
Period	24/04/17 → 27/04/17

Access to Document

10.1109/VLSI-TSA.2017.7942460

Cite this

Lee, H. P., Yu, C. L., You, W. X., & Su, P. (2017). Investigation and comparison of design space for ultra-thin-body GeOI/SOI negative capacitance FETs. In 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017 Article 7942460 (2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-TSA.2017.7942460

Lee, Ho Pei ; Yu, Chien Lin ; You, Wei Xiang et al. / Investigation and comparison of design space for ultra-thin-body GeOI/SOI negative capacitance FETs. 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017. Institute of Electrical and Electronics Engineers Inc., 2017. (2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017).

@inproceedings{f00c6b38c86846a5891350bb8f9a98ef,

title = "Investigation and comparison of design space for ultra-thin-body GeOI/SOI negative capacitance FETs",

abstract = "Using the concept of design space, we have investigated and compared the subthreshold characteristics of UTB NCFETs with Ge/Si channel. Our results indicate that high permittivity channel is more suitable for NCFET design because of the high Cch. Furthermore, as channel length shrinks, the optimal SS of the NCFET becomes smaller due to the drain coupling (CDIBL). In other words, GeOI NCFETs can achieve lower SS than the Si counterpart due to their higher Cch and CDIBL.",

author = "Lee, {Ho Pei} and Yu, {Chien Lin} and You, {Wei Xiang} and Pin Su",

year = "2017",

month = jun,

day = "7",

doi = "10.1109/VLSI-TSA.2017.7942460",

language = "English",

series = "2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017",

address = "美國",

note = "2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017 ; Conference date: 24-04-2017 Through 27-04-2017",

}

Lee, HP, Yu, CL, You, WX & Su, P 2017, Investigation and comparison of design space for ultra-thin-body GeOI/SOI negative capacitance FETs. in 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017., 7942460, 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017, Institute of Electrical and Electronics Engineers Inc., 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017, Hsinchu, Taiwan, 24/04/17. https://doi.org/10.1109/VLSI-TSA.2017.7942460

Investigation and comparison of design space for ultra-thin-body GeOI/SOI negative capacitance FETs. / Lee, Ho Pei; Yu, Chien Lin; You, Wei Xiang et al.
2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017. Institute of Electrical and Electronics Engineers Inc., 2017. 7942460 (2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Investigation and comparison of design space for ultra-thin-body GeOI/SOI negative capacitance FETs

AU - Lee, Ho Pei

AU - Yu, Chien Lin

AU - You, Wei Xiang

AU - Su, Pin

PY - 2017/6/7

Y1 - 2017/6/7

N2 - Using the concept of design space, we have investigated and compared the subthreshold characteristics of UTB NCFETs with Ge/Si channel. Our results indicate that high permittivity channel is more suitable for NCFET design because of the high Cch. Furthermore, as channel length shrinks, the optimal SS of the NCFET becomes smaller due to the drain coupling (CDIBL). In other words, GeOI NCFETs can achieve lower SS than the Si counterpart due to their higher Cch and CDIBL.

AB - Using the concept of design space, we have investigated and compared the subthreshold characteristics of UTB NCFETs with Ge/Si channel. Our results indicate that high permittivity channel is more suitable for NCFET design because of the high Cch. Furthermore, as channel length shrinks, the optimal SS of the NCFET becomes smaller due to the drain coupling (CDIBL). In other words, GeOI NCFETs can achieve lower SS than the Si counterpart due to their higher Cch and CDIBL.

UR - http://www.scopus.com/inward/record.url?scp=85023186476&partnerID=8YFLogxK

U2 - 10.1109/VLSI-TSA.2017.7942460

DO - 10.1109/VLSI-TSA.2017.7942460

M3 - Conference contribution

AN - SCOPUS:85023186476

T3 - 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017

BT - 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017

Y2 - 24 April 2017 through 27 April 2017

ER -

Lee HP, Yu CL, You WX, Su P. Investigation and comparison of design space for ultra-thin-body GeOI/SOI negative capacitance FETs. In 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017. Institute of Electrical and Electronics Engineers Inc. 2017. 7942460. (2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017). doi: 10.1109/VLSI-TSA.2017.7942460

Investigation and comparison of design space for ultra-thin-body GeOI/SOI negative capacitance FETs

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this