Inversion MOS capacitance extraction for ultra-thin gate oxide using BSIM4

Wei Lee; Ke Wei Su; Chung Shi Chiang; Sally Liu; Pin Su

doi:10.1109/VTSA.2005.1497081

Inversion MOS capacitance extraction for ultra-thin gate oxide using BSIM4

Wei Lee^*, Ke Wei Su, Chung Shi Chiang, Sally Liu, Pin Su

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Original language	English
Title of host publication	2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers
Pages	62-63
Number of pages	2
DOIs	https://doi.org/10.1109/VTSA.2005.1497081
State	Published - 31 Oct 2005
Event	2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH - Hsinchu, Taiwan Duration: 25 Apr 2005 → 27 Apr 2005

Publication series

Name	2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers

Conference

Conference	2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH
Country/Territory	Taiwan
City	Hsinchu
Period	25/04/05 → 27/04/05

Access to Document

10.1109/VTSA.2005.1497081

Cite this

Lee, W., Su, K. W., Chiang, C. S., Liu, S., & Su, P. (2005). Inversion MOS capacitance extraction for ultra-thin gate oxide using BSIM4. In 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers (pp. 62-63). (2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers). https://doi.org/10.1109/VTSA.2005.1497081

Lee, Wei ; Su, Ke Wei ; Chiang, Chung Shi et al. / Inversion MOS capacitance extraction for ultra-thin gate oxide using BSIM4. 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers. 2005. pp. 62-63 (2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers).

@inproceedings{349ba614f9994964afee03b1ceaa8e6c,

title = "Inversion MOS capacitance extraction for ultra-thin gate oxide using BSIM4",

author = "Wei Lee and Su, {Ke Wei} and Chiang, {Chung Shi} and Sally Liu and Pin Su",

year = "2005",

month = oct,

day = "31",

doi = "10.1109/VTSA.2005.1497081",

language = "English",

isbn = "078039058X",

series = "2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers",

pages = "62--63",

booktitle = "2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers",

note = "2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH ; Conference date: 25-04-2005 Through 27-04-2005",

}

Lee, W, Su, KW, Chiang, CS, Liu, S & Su, P 2005, Inversion MOS capacitance extraction for ultra-thin gate oxide using BSIM4. in 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers. 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers, pp. 62-63, 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Hsinchu, Taiwan, 25/04/05. https://doi.org/10.1109/VTSA.2005.1497081

Inversion MOS capacitance extraction for ultra-thin gate oxide using BSIM4. / Lee, Wei; Su, Ke Wei; Chiang, Chung Shi et al.
2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers. 2005. p. 62-63 (2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Inversion MOS capacitance extraction for ultra-thin gate oxide using BSIM4

AU - Lee, Wei

AU - Su, Ke Wei

AU - Chiang, Chung Shi

AU - Liu, Sally

AU - Su, Pin

PY - 2005/10/31

Y1 - 2005/10/31

UR - http://www.scopus.com/inward/record.url?scp=27144519597&partnerID=8YFLogxK

U2 - 10.1109/VTSA.2005.1497081

DO - 10.1109/VTSA.2005.1497081

M3 - Conference contribution

AN - SCOPUS:27144519597

SN - 078039058X

T3 - 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers

SP - 62

EP - 63

BT - 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers

T2 - 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH

Y2 - 25 April 2005 through 27 April 2005

ER -

Lee W, Su KW, Chiang CS, Liu S, Su P. Inversion MOS capacitance extraction for ultra-thin gate oxide using BSIM4. In 2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA - TECH, Proceedings of Technical Papers. 2005. p. 62-63. (2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers). doi: 10.1109/VTSA.2005.1497081

Inversion MOS capacitance extraction for ultra-thin gate oxide using BSIM4

Publication series

Conference

Access to Document

Other files and links

Cite this