Intrinsic Difference between 2-D Negative-Capacitance FETs with Semiconductor-on-Insulator and Double-Gate Structures

Wei Xiang You, Pin Su*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

12 Scopus citations


With the aid of an analytical and general model, this paper investigates the intrinsic difference in the negative-capacitance (NC) effect and design space between semiconductor-on-insulator (SOI) and double-gate (DG) metal-ferroelectric-insulator-semiconductor-type NC field-effect transistors (NCFETs) with a 2-D semiconducting transition-metal-dichalcogenide channel (2-D NCFET). By examining the distributions of internal charge, voltage gain, and capacitance matching over the whole bias range, the intrinsic difference in NC effects between these two topologies is pointed out and explained. Our study indicates that for an intrinsic DG 2-D NCFET, it is difficult to achieve sub-2.3 kT/q average subthreshold swing (SS). By contrast, the bias-dependent subthreshold internal charge and larger curvature of ferroelectric capacitance due to the independent backgate in the SOI 2-D NCFET enable larger design space and sub-2.3 kT/q average SS, making it more suitable for low-power applications.

Original languageEnglish
Article number8454292
Pages (from-to)4196-4201
Number of pages6
JournalIEEE Transactions on Electron Devices
Issue number10
StatePublished - 1 Oct 2018


  • 2-D semiconductors
  • Landau-Khalatnikov (L-K) equation
  • double-gate (DG)
  • ferroelectric field-effect transistor (FET)
  • metal-ferroelectric-insulator-semiconductor (MFIS)-type negative-capacitance (NC) FET (NCFET)
  • semiconductor-on-insulator (SOI)
  • transition-metal-dichalcogenide (TMD)


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