Abstract
Statistical analysis of an advanced CMOS process reveals a significant systematic within-field variability of gate CD strongly dependent on the local layout patterns. We present a novel modeling methodology for accurate prediction of the effect of such CD variability on circuit performance that enables statistical design for increased performance and yield. We also propose a mask-level gate CD correction algorithm allowing significant reduction of overall variability and provide a model to evaluate the effectiveness of correction.
| Original language | English |
|---|---|
| Pages (from-to) | 479-482 |
| Number of pages | 4 |
| Journal | Technical Digest - International Electron Devices Meeting |
| DOIs | |
| State | Published - 1999 |
| Event | 1999 IEEE International Devices Meeting (IEDM) - Washington, DC, USA Duration: 5 Dec 1999 → 8 Dec 1999 |
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