Integration of millisecond flash anneal on CMOS devices for DRAM manufacturing

Shian Jyh Lin*, Chao Sung Lai, Sheng Tsung Chen, Yi Jung Chen, Brady Huang, Neng Tai Shih, Chung Yuan Lee, Pei Ing Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

We successfully demonstrate the millisecond flash anneal (MFLA) on a matured DRAM product. The GIDL improvements for array NMOS, periphery N and P MOS are 14.5%, 15%, and 39% respectively. The mechanisms of GIDL impact at different process stages have been reviewed. With MFLA replacement, N and PMOS on-current (Ioff) gains 4.3% and 11.8% respectively. Superior off current (Ioff) reduction for periphery N and PMOS reach 150% and 500% respectively. Vt roll-off, Vt-Ion, Ion-Ioff correlation, overlap capacitance, and drain induced barrier lowering (DIBL) have been reviewed. TEM data show poly grain enlargement and clustering defects staying at different junction depths. This study shows that MFLA has the benefit for lower thermal budget, high dopant activation, and shallow junction for sub-50nm DRAM.

Original languageEnglish
Title of host publication2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA
Pages99-100
Number of pages2
DOIs
StatePublished - 2008
Event2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA - Hsinchu, Taiwan
Duration: 21 Apr 200823 Apr 2008

Publication series

NameInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings

Conference

Conference2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA
Country/TerritoryTaiwan
CityHsinchu
Period21/04/0823/04/08

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