Integration of high-k gate stack systems into planar CMOS process flows

H. R. Huff; A. Agarwal; Y. Kim; L. Perrymore; D. Riley; J. Barnett; C. Sparks; M. Freiler; G. Gebara; B. Bowers; P. J. Chen; P. Lysaght; B. Nguyen; J. E. Lim; S. Lim; G. Bersuker; P. Zeitzoff; G. A. Brown; C. Young; B. Foran; F. Shaapur; Tuo-Hung Hou; C. Lim; H. Alshareef; S. Borthakur; D. J. Derro; R. Bergmann; L. A. Larson; M. I. Gardner; J. Gutt; R. W. Murto; K. Torres; M. D. Jackson

doi:10.1109/IWGI.2001.967538

Integration of high-k gate stack systems into planar CMOS process flows

H. R. Huff, A. Agarwal, Y. Kim, L. Perrymore, D. Riley, J. Barnett, C. Sparks, M. Freiler, G. Gebara, B. Bowers, P. J. Chen, P. Lysaght, B. Nguyen, J. E. Lim, S. Lim, G. Bersuker, P. Zeitzoff, G. A. Brown, C. Young, B. ForanF. Shaapur, Tuo-Hung Hou, C. Lim, H. Alshareef, S. Borthakur, D. J. Derro, R. Bergmann, L. A. Larson, M. I. Gardner, J. Gutt, R. W. Murto, K. Torres, M. D. Jackson

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

19 Scopus citations

Abstract

We review several gate stack fabrication issues critical for robust, commercially viable tools, including assessment of possible fab contamination due to the higher-k gate dielectrics and the role of subsequent thermal procedures during, for example, source/drain anneals (including the importance of the oxygen partial pressure) to ensure their compatibility with conventional planar polysilicon CMOS transistor fabrication processes.

Original language	English
Title of host publication	Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	2-11
Number of pages	10
ISBN (Electronic)	4891140216, 9784891140212
DOIs	https://doi.org/10.1109/IWGI.2001.967538
State	Published - 2001
Event	International Workshop on Gate Insulator, IWGI 2001 - Tokyo, Japan Duration: 1 Nov 2001 → 2 Nov 2001

Publication series

Name	Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001

Conference

Conference	International Workshop on Gate Insulator, IWGI 2001
Country/Territory	Japan
City	Tokyo
Period	1/11/01 → 2/11/01

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10.1109/IWGI.2001.967538

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Huff, H. R., Agarwal, A., Kim, Y., Perrymore, L., Riley, D., Barnett, J., Sparks, C., Freiler, M., Gebara, G., Bowers, B., Chen, P. J., Lysaght, P., Nguyen, B., Lim, J. E., Lim, S., Bersuker, G., Zeitzoff, P., Brown, G. A., Young, C., ... Jackson, M. D. (2001). Integration of high-k gate stack systems into planar CMOS process flows. In Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001 (pp. 2-11). Article 967538 (Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IWGI.2001.967538

@inproceedings{053ba1d2835d44b2b2277cf326226087,

title = "Integration of high-k gate stack systems into planar CMOS process flows",

abstract = "We review several gate stack fabrication issues critical for robust, commercially viable tools, including assessment of possible fab contamination due to the higher-k gate dielectrics and the role of subsequent thermal procedures during, for example, source/drain anneals (including the importance of the oxygen partial pressure) to ensure their compatibility with conventional planar polysilicon CMOS transistor fabrication processes.",

author = "Huff, {H. R.} and A. Agarwal and Y. Kim and L. Perrymore and D. Riley and J. Barnett and C. Sparks and M. Freiler and G. Gebara and B. Bowers and Chen, {P. J.} and P. Lysaght and B. Nguyen and Lim, {J. E.} and S. Lim and G. Bersuker and P. Zeitzoff and Brown, {G. A.} and C. Young and B. Foran and F. Shaapur and Tuo-Hung Hou and C. Lim and H. Alshareef and S. Borthakur and Derro, {D. J.} and R. Bergmann and Larson, {L. A.} and Gardner, {M. I.} and J. Gutt and Murto, {R. W.} and K. Torres and Jackson, {M. D.}",

note = "Publisher Copyright: {\textcopyright} 2001 Japan Soc of Applied Physics.; International Workshop on Gate Insulator, IWGI 2001 ; Conference date: 01-11-2001 Through 02-11-2001",

year = "2001",

doi = "10.1109/IWGI.2001.967538",

language = "English",

series = "Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "2--11",

booktitle = "Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001",

address = "United States",

}

Huff, HR, Agarwal, A, Kim, Y, Perrymore, L, Riley, D, Barnett, J, Sparks, C, Freiler, M, Gebara, G, Bowers, B, Chen, PJ, Lysaght, P, Nguyen, B, Lim, JE, Lim, S, Bersuker, G, Zeitzoff, P, Brown, GA, Young, C, Foran, B, Shaapur, F, Hou, T-H, Lim, C, Alshareef, H, Borthakur, S, Derro, DJ, Bergmann, R, Larson, LA, Gardner, MI, Gutt, J, Murto, RW, Torres, K & Jackson, MD 2001, Integration of high-k gate stack systems into planar CMOS process flows. in Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001., 967538, Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001, Institute of Electrical and Electronics Engineers Inc., pp. 2-11, International Workshop on Gate Insulator, IWGI 2001, Tokyo, Japan, 1/11/01. https://doi.org/10.1109/IWGI.2001.967538

Integration of high-k gate stack systems into planar CMOS process flows. / Huff, H. R.; Agarwal, A.; Kim, Y. et al.
Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001. Institute of Electrical and Electronics Engineers Inc., 2001. p. 2-11 967538 (Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Integration of high-k gate stack systems into planar CMOS process flows

AU - Huff, H. R.

AU - Agarwal, A.

AU - Kim, Y.

AU - Perrymore, L.

AU - Riley, D.

AU - Barnett, J.

AU - Sparks, C.

AU - Freiler, M.

AU - Gebara, G.

AU - Bowers, B.

AU - Chen, P. J.

AU - Lysaght, P.

AU - Nguyen, B.

AU - Lim, J. E.

AU - Lim, S.

AU - Bersuker, G.

AU - Zeitzoff, P.

AU - Brown, G. A.

AU - Young, C.

AU - Foran, B.

AU - Shaapur, F.

AU - Hou, Tuo-Hung

AU - Lim, C.

AU - Alshareef, H.

AU - Borthakur, S.

AU - Derro, D. J.

AU - Bergmann, R.

AU - Larson, L. A.

AU - Gardner, M. I.

AU - Gutt, J.

AU - Murto, R. W.

AU - Torres, K.

AU - Jackson, M. D.

PY - 2001

Y1 - 2001

N2 - We review several gate stack fabrication issues critical for robust, commercially viable tools, including assessment of possible fab contamination due to the higher-k gate dielectrics and the role of subsequent thermal procedures during, for example, source/drain anneals (including the importance of the oxygen partial pressure) to ensure their compatibility with conventional planar polysilicon CMOS transistor fabrication processes.

AB - We review several gate stack fabrication issues critical for robust, commercially viable tools, including assessment of possible fab contamination due to the higher-k gate dielectrics and the role of subsequent thermal procedures during, for example, source/drain anneals (including the importance of the oxygen partial pressure) to ensure their compatibility with conventional planar polysilicon CMOS transistor fabrication processes.

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U2 - 10.1109/IWGI.2001.967538

DO - 10.1109/IWGI.2001.967538

M3 - Conference contribution

AN - SCOPUS:84954160798

T3 - Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001

SP - 2

EP - 11

BT - Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - International Workshop on Gate Insulator, IWGI 2001

Y2 - 1 November 2001 through 2 November 2001

ER -

Huff HR, Agarwal A, Kim Y, Perrymore L, Riley D, Barnett J et al. Integration of high-k gate stack systems into planar CMOS process flows. In Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001. Institute of Electrical and Electronics Engineers Inc. 2001. p. 2-11. 967538. (Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001). doi: 10.1109/IWGI.2001.967538

Integration of high-k gate stack systems into planar CMOS process flows

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