Skip to main navigation Skip to search Skip to main content

Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size

  • X. R. Yu*
  • , M. H. Chuang
  • , S. W. Chang
  • , W. H. Chang
  • , T. C. Hong
  • , C. H. Chiang
  • , W. H. Lu
  • , C. Y. Yang
  • , W. J. Chen
  • , J. H. Lin
  • , P. H. Wu
  • , T. C. Sun
  • , S. Kola
  • , Y. S. Yang
  • , Yun Da
  • , P. J. Sung
  • , C. T. Wu
  • , T. C. Cho
  • , G. L. Luo
  • , K. H. Kao
    • M. H. Chiang, W. C.Y. Ma, C. J. Su, T. S. Chao, T. Maeda, S. Samukawa, Y. Li, Y. J. Lee, W. F. Wu, J. H. Tarng, Y. H. Wang
*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

21 Scopus citations

Fingerprint

Dive into the research topics of 'Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size'. Together they form a unique fingerprint.
Sort by

Keyphrases

Engineering