@inproceedings{29c2e426451e4ec0b3507929ad53f65d,
title = "Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42\% Reduced Cell Size",
abstract = "In this work, we propose an advanced 3-D heterogeneous 6T SRAM with a newly designed hetero-integration method. CFET inverters and IGZO pass gates are vertically stacked within a 2T footprint area. The Low-Temperature Hetero-Layers Bonding Technique (LT-HBT) process is utilized successfully to fabricate single crystalline heterogeneous Double Layer Transferred (DLT) Ge/2Si CFET-OI on an 8-inch full wafer. Furthermore, an IGZO nFET is deposited and treated as a pass gate (PG) to realize a 6T SRAM operation. The hetero-integration of IGZO PG and self-align DLT Ge/2Si CFET inverters showed improved Read Static Noise Margin (RSNM) and stand-by leakage power. The state-of-the-art 3-D heterogeneous 6T SRAM leads to 42\% area reduction.",
author = "Yu, \{X. R.\} and Chuang, \{M. H.\} and Chang, \{S. W.\} and Chang, \{W. H.\} and Hong, \{T. C.\} and Chiang, \{C. H.\} and Lu, \{W. H.\} and Yang, \{C. Y.\} and Chen, \{W. J.\} and Lin, \{J. H.\} and Wu, \{P. H.\} and Sun, \{T. C.\} and S. Kola and Yang, \{Y. S.\} and Yun Da and Sung, \{P. J.\} and Wu, \{C. T.\} and Cho, \{T. C.\} and Luo, \{G. L.\} and Kao, \{K. H.\} and Chiang, \{M. H.\} and Ma, \{W. C.Y.\} and Su, \{C. J.\} and Chao, \{T. S.\} and T. Maeda and S. Samukawa and Y. Li and Lee, \{Y. J.\} and Wu, \{W. F.\} and Tarng, \{J. H.\} and Wang, \{Y. H.\}",
note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 International Electron Devices Meeting, IEDM 2022 ; Conference date: 03-12-2022 Through 07-12-2022",
year = "2022",
doi = "10.1109/IEDM45625.2022.10019507",
language = "English",
series = "Technical Digest - International Electron Devices Meeting, IEDM",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "2051--2054",
booktitle = "2022 International Electron Devices Meeting, IEDM 2022",
address = "美國",
}