TY - GEN
T1 - Integrating compiler and system toolkit flow for embedded VLIW DSP processors
AU - Wu, Chi
AU - Hsieh, Kun Yuan
AU - Lin, Yung Chia
AU - Wu, Chung Ju
AU - Shih, Wen Li
AU - Chen, S. C.
AU - Chen, Chung Kai
AU - Huang, Chien Ching
AU - You, Yi-Ping
AU - Lee, Jenq Kuen
PY - 2006/12/1
Y1 - 2006/12/1
N2 - To support high-performance and low-power for multimedia applications and for hand-held devices, embedded VLIW DSP processors are of research focus. With the tight resource constraints, distributed register files, variable-length encodings for instructions, and special data paths are frequently adopted. This creates challenges to deploy software toolkits for new embedded DSP processors. This article presents our methods and experiences to develop software and toolkit flows for PAC (Parallel Architecture Core) VLIW DSP processors. Our toolkits include compilers, assemblers, debugger, and DSP micro-kernels. We first retarget Open Research Compiler (ORC) and toolkit chains for PAC VLIW DSP processor and address the issues to support distributed register files and ping-pong data paths for embedded VLIW DSP processors. Second, the linker and assmeber are able to support variable length encoding schemes for DSP instructions. In addition, the debugger and DSP micro-kernel were designed to handle dualcore environments. The footprint of micro-kernel is also around 10K to address the code-size issues for embedded devices. We also present the experimental result in the compiler framework by incorporating software pipeline (SWP) policies for distributed register files in PAC architecture. Results indicated that our compiler framework gains performance improvement around 2.5 times against the code generated without our proposed optimizations.
AB - To support high-performance and low-power for multimedia applications and for hand-held devices, embedded VLIW DSP processors are of research focus. With the tight resource constraints, distributed register files, variable-length encodings for instructions, and special data paths are frequently adopted. This creates challenges to deploy software toolkits for new embedded DSP processors. This article presents our methods and experiences to develop software and toolkit flows for PAC (Parallel Architecture Core) VLIW DSP processors. Our toolkits include compilers, assemblers, debugger, and DSP micro-kernels. We first retarget Open Research Compiler (ORC) and toolkit chains for PAC VLIW DSP processor and address the issues to support distributed register files and ping-pong data paths for embedded VLIW DSP processors. Second, the linker and assmeber are able to support variable length encoding schemes for DSP instructions. In addition, the debugger and DSP micro-kernel were designed to handle dualcore environments. The footprint of micro-kernel is also around 10K to address the code-size issues for embedded devices. We also present the experimental result in the compiler framework by incorporating software pipeline (SWP) policies for distributed register files in PAC architecture. Results indicated that our compiler framework gains performance improvement around 2.5 times against the code generated without our proposed optimizations.
UR - http://www.scopus.com/inward/record.url?scp=34547365277&partnerID=8YFLogxK
U2 - 10.1109/RTCSA.2006.40|
DO - 10.1109/RTCSA.2006.40|
M3 - Conference contribution
AN - SCOPUS:34547365277
SN - 0769526764
SN - 9780769526768
T3 - Proceedings - 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2006
SP - 215
EP - 222
BT - 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2006
T2 - 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2006
Y2 - 16 August 2006 through 18 August 2006
ER -