Integrated GaN HEMT Cascode Power Module Stability Analysis under Negative Gate Bias Stress for Power Electronic Applications

Surya Elangovan*, Wen Yea Jang, Stone Cheng, Jia Hao Yao

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

Abstract

We present a detailed investigation of two forms of negative gate bias stress in four parallel GaN HEMTs in cascode configuration in this article: (i) pulsed off-state gate bias and (ii) negative bias temperature instability (NBTI). Device statical parameter degradations and instabilities, such as IDS, RDS-ON, GM, max, and IGSS, are evident under low/mid pulsed off-state gate bias stress conditions, according to the measured results of pulsed gate bias stress. Under NBTI experiments, mid/high off-state bias stress with accelerated temperatures, the device demonstrated their excellent stability and negligible degradation of VTHand RDS-ON. These findings pave the way for evaluating device reliability and understanding the failure mechanism caused by negative gate bias stress, allowing emerging GaN cascode technologies to advance faster.

Original languageEnglish
Pages (from-to)282-286
Number of pages5
JournalIFAC-PapersOnLine
Volume55
Issue number27
DOIs
StatePublished - 1 Sep 2022
Event9th IFAC Symposium on Mechatronic Systems, MECHATRONICS 2022 - Los Angeles, United States
Duration: 6 Sep 20229 Sep 2022

Keywords

  • Cascode Power Module
  • GaN HEMT
  • Gate Bias Stress
  • Rinstability
  • V

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