Instruction set extension exploration in multiple-issue architecture

I. Wei Wu*, Zhi Yuan Chen, Jyh-Jiun Shann, Chung-Ping Chung

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations


To satisfy high-performance computing demand in modern embedded devices, current embedded processor architectures provide designer with possibility either to define customized instruction set extension (ISE) or to increase instruction issue width. Previous studies have shown that deploying ISE in multiple-issue architecture can significantly improve performance. However, identifying ISE for multiple-issue architecture by using current ISE exploration algorithms will result in unnecessary waste of silicon area and limitation of performance improvement. This is because most algorithms overlook two important considerations: (1) only packing the operations lying on the critical path into ISE can improve performance; (2) the critical path usually changes after packing operations into an ISE. With these considerations, this paper presents an algorithm for ISE exploration based on list scheduling and Ant Colony Optimization (ACO), in which combines ISE exploration and the critical path identification (i.e. instruction scheduling). Results indicate that our approach outperforms the previous work in both performance improvement and area efficiency.

Original languageEnglish
Title of host publicationDesign, Automation and Test in Europe, DATE 2008
Number of pages6
StatePublished - 25 Aug 2008
EventDesign, Automation and Test in Europe, DATE 2008 - Munich, Germany
Duration: 10 Mar 200814 Mar 2008

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591


ConferenceDesign, Automation and Test in Europe, DATE 2008


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