Instruction-cycle-based dynamic voltage scaling power management for low-power digital signal processor with 53% power savings

Shen Yu Peng, Tzu Chi Huang, Yu Huei Lee, Chao Chang Chiu, Ke-Horng Chen, Ying Hsi Lin, Chao Cheng Lee, Tsung Yen Tsai, Chen Chih Huang, Long Der Chen, Cheng Chen Yang

Research output: Contribution to journalArticlepeer-review

11 Scopus citations


This paper presents and analyzes a fully digital instruction-cycle-based dynamic voltage scaling (iDVS) power management strategy for low-power processor designs. The proposed iDVS technique is fully compatible with conventional DVS scheduler algorithms. An additional computer aided design-based design flow was embedded in a standard cell library to implement the iDVS-based processor in highly integrated system-on-a-chip applications. The lattice asynchronous self-timed control digital low-dropout regulator with swift response and low quiescent current was also utilized to improve iDVS voltage transition response. Results show that the iDVS-based processor with the proposed adaptive instruction cycle control scheme can efficiently perform millions of instructions per second during iDVS transition. The iDVS-based digital signal processor chip was implemented in a HH-NEC 0.18-μm standard complementary metal-oxide semiconductor. Measurement results show that the voltage tracking speed with 11.6 Vμs saved 53% power.

Original languageEnglish
Article number6578600
Number of pages1
JournalIEEE Journal of Solid-State Circuits
Issue number11
StatePublished - 19 Aug 2013


  • Buck converter
  • Digital signal processor (DSP)
  • Dynamic voltage scaling (DVS)
  • Fast transient
  • Low dropout (LDO) regulator
  • Low-power design
  • Million instructions per second (MIPS) performance
  • SoC
  • Switching regulator


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