Innovative Recovery Strategy for MFIS-FeFETs at Optimal Timing With Robust Endurance: Fast-Unipolar Pulsing (100 ns), Nearly Zero Memory Window Loss (0.02%), and Self-Tracking Circuit Design

Cheng Hung Wu, Jay Liu, Xun Ting Zheng, Han Fu Chuang, Yi Ming Tseng, Masaharu Kobayashi, Chun Jung Su*, Vita Pi Ho Hu*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

This work systematically demonstrates a novel recovery scheme for metal-ferroelectric-insulator-semiconductor (MFIS) ferroelectric field-effect transistor (FeFET) memory arrays involving device fabrication, memory operation, and circuit integration. For the first time, the timing to initiate recovery to prolong the endurance of FeFETs is studied. A 100-ns fast-unipolar pulsing (FUP) recovery treatment at optimized timing is exhibited, significantly extending endurance cycles by a factor of 10{{2}} , together with a nearly zero loss (0.02%) in memory window (MW) per recovery period and a reduced MW fluctuation. An ultralow recovery-induced time loss ratio of 5times 10{-{5}} % is achieved. Based on the developed scheme, we propose a self-tracking recovery circuit design utilizing current-mode memory sensing to monitor the degree of fatigue and automatically trigger the recovery operation.

Original languageEnglish
Pages (from-to)3371-3376
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume71
Issue number5
DOIs
StatePublished - 1 May 2024

Keywords

  • Endurance
  • ferroelectric field-effect transistors (FeFETs)
  • interface optimization
  • nonvolatile
  • recovery

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