Initial-on BSD protection design with PMO S-triggered SCR device

Ming Dou Ker; Shih Hung Chen

doi:10.1109/ASSCC.2005.251818

Initial-on BSD protection design with PMO S-triggered SCR device

Ming Dou Ker^*, Shih Hung Chen

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

A novel SCR design with "initial-on" function is proposed to achieve the lowest trigger voltage and the fastest turn-on speed of SCR device for effective on-chip ESD protection. Without using the special native device or any process modification, this initial-on design is implemented by PMOS-triggered SCR device, which can be realized in general CMOS processes. This initial-on SCR design also presents a high enough holding voltage to avoid latchup issue. The new proposed initial-on ESD protection design with PMOS-triggered SCR device has been successfully verified in a 0.25-μm CMOS process.

Original language	English
Title of host publication	2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005
Publisher	IEEE Computer Society
Pages	105-108
Number of pages	4
ISBN (Print)	0780391624, 9780780391628
DOIs	https://doi.org/10.1109/ASSCC.2005.251818
State	Published - 1 Jan 2005
Event	1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005 - Hsinchu, Taiwan Duration: 1 Nov 2005 → 3 Nov 2005

Publication series

Name	2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005

Conference

Conference	1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005
Country/Territory	Taiwan
City	Hsinchu
Period	1/11/05 → 3/11/05

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10.1109/ASSCC.2005.251818

Cite this

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title = "Initial-on BSD protection design with PMO S-triggered SCR device",

abstract = "A novel SCR design with {"}initial-on{"} function is proposed to achieve the lowest trigger voltage and the fastest turn-on speed of SCR device for effective on-chip ESD protection. Without using the special native device or any process modification, this initial-on design is implemented by PMOS-triggered SCR device, which can be realized in general CMOS processes. This initial-on SCR design also presents a high enough holding voltage to avoid latchup issue. The new proposed initial-on ESD protection design with PMOS-triggered SCR device has been successfully verified in a 0.25-μm CMOS process.",

author = "Ker, {Ming Dou} and Chen, {Shih Hung}",

year = "2005",

month = jan,

day = "1",

doi = "10.1109/ASSCC.2005.251818",

language = "English",

isbn = "0780391624",

series = "2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005",

publisher = "IEEE Computer Society",

pages = "105--108",

booktitle = "2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005",

address = "美國",

note = "1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005 ; Conference date: 01-11-2005 Through 03-11-2005",

}

Ker, MD & Chen, SH 2005, Initial-on BSD protection design with PMO S-triggered SCR device. in 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005., 4017542, 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005, IEEE Computer Society, pp. 105-108, 1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005, Hsinchu, Taiwan, 1/11/05. https://doi.org/10.1109/ASSCC.2005.251818

Initial-on BSD protection design with PMO S-triggered SCR device. / Ker, Ming Dou; Chen, Shih Hung.
2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005. IEEE Computer Society, 2005. p. 105-108 4017542 (2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - A novel SCR design with "initial-on" function is proposed to achieve the lowest trigger voltage and the fastest turn-on speed of SCR device for effective on-chip ESD protection. Without using the special native device or any process modification, this initial-on design is implemented by PMOS-triggered SCR device, which can be realized in general CMOS processes. This initial-on SCR design also presents a high enough holding voltage to avoid latchup issue. The new proposed initial-on ESD protection design with PMOS-triggered SCR device has been successfully verified in a 0.25-μm CMOS process.

AB - A novel SCR design with "initial-on" function is proposed to achieve the lowest trigger voltage and the fastest turn-on speed of SCR device for effective on-chip ESD protection. Without using the special native device or any process modification, this initial-on design is implemented by PMOS-triggered SCR device, which can be realized in general CMOS processes. This initial-on SCR design also presents a high enough holding voltage to avoid latchup issue. The new proposed initial-on ESD protection design with PMOS-triggered SCR device has been successfully verified in a 0.25-μm CMOS process.

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BT - 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005

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T2 - 1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005

Y2 - 1 November 2005 through 3 November 2005

ER -

Initial-on BSD protection design with PMO S-triggered SCR device

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