@inproceedings{1bbe049d3f5443e2a6b8b418bf4f721a,
title = "Incremental ADC with parallel counting",
abstract = "An incremental ADC (lADC) using parallel counting is proposed to achieve both high accuracy and power efficiency. By operating the IADC and the counting logic alternatively within two clock phases, the proposed scheme finishes a full conversion within fewer conversion cycles. The only additional circuitry for the parallel counting is a single comparator, much less than the add-ons in other multi-step topologies. Also, the parallel counting technique can be implemented with different IADC topologies.",
keywords = "Analog-to-digital converter, Delta sigma modulator, Extended data converters, High resolution, Incremental data converters, Sensor interfaces, Ultra-low-power",
author = "Tao He and Chia-Hung Chen and Yi Zhang and Temes, {Gabor C.}",
note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017 ; Conference date: 06-08-2017 Through 09-08-2017",
year = "2017",
month = sep,
day = "27",
doi = "10.1109/MWSCAS.2017.8053099",
language = "English",
series = "Midwest Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1017--1020",
booktitle = "2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017",
address = "United States",
}