Increasing PE Utilization with a SW/HW Co-Design Technique for Sparse Convolutional Neural Networks

Wei Fan Tseng; Bo Cheng Lai; Jyun Wei Pan

doi:10.1109/ICICE49024.2019.9117552

Increasing PE Utilization with a SW/HW Co-Design Technique for Sparse Convolutional Neural Networks

Wei Fan Tseng
, Bo Cheng Lai
, Jyun Wei Pan

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

Pruning convolution neural networks (CNN) has proved to be an effective technique to decrease the network size without loss of accuracy. By processing the compressed format of the network, the energy consumption can be considerably reduced. However, the existing SIMD-like sparse CNN accelerator suffers from low processing engine (PE) utilization due to the irregular distribution of effectual pairs. In this paper, we address this issue by proposing a software and hardware codesign technique, including a novel data compression scheme and a dedicated module to handle this compressed format. When compared to a state-of-the-art SIMD-like accelerator, the proposed co-design technique can reduce the computation time of conv3, conv4, conv5 of AlexNet by 15%, 33%, 31%.

Original language	English
Title of host publication	Proceedings of the 2019 8th International Conference on Innovation, Communication and Engineering, ICICE 2019
Editors	Shoou-Jinn Chang, Sheng-Joue Young, Artde Donald Kin-Tak Lam, Liang-Wen Ji, Hao-Ying Lu, Stephen D. Prior
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	74-77
Number of pages	4
ISBN (Electronic)	9781728158396
DOIs	https://doi.org/10.1109/ICICE49024.2019.9117552
State	Published - Oct 2019
Event	8th International Conference on Innovation, Communication and Engineering, ICICE 2019 - Zhengzhou, Henan Province, China Duration: 25 Oct 2019 → 30 Oct 2019

Publication series

Name	Proceedings of the 2019 8th International Conference on Innovation, Communication and Engineering, ICICE 2019

Conference

Conference	8th International Conference on Innovation, Communication and Engineering, ICICE 2019
Country/Territory	China
City	Zhengzhou, Henan Province
Period	25/10/19 → 30/10/19

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Machine learning
SIMD architecture
Sparse convolution neural networks

Access to Document

10.1109/ICICE49024.2019.9117552

Cite this

Tseng, W. F., Lai, B. C., & Pan, J. W. (2019). Increasing PE Utilization with a SW/HW Co-Design Technique for Sparse Convolutional Neural Networks. In S.-J. Chang, S.-J. Young, A. D. K.-T. Lam, L.-W. Ji, H.-Y. Lu, & S. D. Prior (Eds.), Proceedings of the 2019 8th International Conference on Innovation, Communication and Engineering, ICICE 2019 (pp. 74-77). Article 9117552 (Proceedings of the 2019 8th International Conference on Innovation, Communication and Engineering, ICICE 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICICE49024.2019.9117552

Tseng, Wei Fan ; Lai, Bo Cheng ; Pan, Jyun Wei. / Increasing PE Utilization with a SW/HW Co-Design Technique for Sparse Convolutional Neural Networks. Proceedings of the 2019 8th International Conference on Innovation, Communication and Engineering, ICICE 2019. editor / Shoou-Jinn Chang ; Sheng-Joue Young ; Artde Donald Kin-Tak Lam ; Liang-Wen Ji ; Hao-Ying Lu ; Stephen D. Prior. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 74-77 (Proceedings of the 2019 8th International Conference on Innovation, Communication and Engineering, ICICE 2019).

@inproceedings{0764ba9f5910410187350704dc358cd8,

title = "Increasing PE Utilization with a SW/HW Co-Design Technique for Sparse Convolutional Neural Networks",

abstract = "Pruning convolution neural networks (CNN) has proved to be an effective technique to decrease the network size without loss of accuracy. By processing the compressed format of the network, the energy consumption can be considerably reduced. However, the existing SIMD-like sparse CNN accelerator suffers from low processing engine (PE) utilization due to the irregular distribution of effectual pairs. In this paper, we address this issue by proposing a software and hardware codesign technique, including a novel data compression scheme and a dedicated module to handle this compressed format. When compared to a state-of-the-art SIMD-like accelerator, the proposed co-design technique can reduce the computation time of conv3, conv4, conv5 of AlexNet by 15\%, 33\%, 31\%.",

keywords = "Machine learning, SIMD architecture, Sparse convolution neural networks",

author = "Tseng, \{Wei Fan\} and Lai, \{Bo Cheng\} and Pan, \{Jyun Wei\}",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE. Copyright: Copyright 2020 Elsevier B.V., All rights reserved.; 8th International Conference on Innovation, Communication and Engineering, ICICE 2019 ; Conference date: 25-10-2019 Through 30-10-2019",

year = "2019",

month = oct,

doi = "10.1109/ICICE49024.2019.9117552",

language = "English",

series = "Proceedings of the 2019 8th International Conference on Innovation, Communication and Engineering, ICICE 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "74--77",

editor = "Shoou-Jinn Chang and Sheng-Joue Young and Lam, \{Artde Donald Kin-Tak\} and Liang-Wen Ji and Hao-Ying Lu and Prior, \{Stephen D.\}",

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address = "美國",

}

Tseng, WF, Lai, BC & Pan, JW 2019, Increasing PE Utilization with a SW/HW Co-Design Technique for Sparse Convolutional Neural Networks. in S-J Chang, S-J Young, ADK-T Lam, L-W Ji, H-Y Lu & SD Prior (eds), Proceedings of the 2019 8th International Conference on Innovation, Communication and Engineering, ICICE 2019., 9117552, Proceedings of the 2019 8th International Conference on Innovation, Communication and Engineering, ICICE 2019, Institute of Electrical and Electronics Engineers Inc., pp. 74-77, 8th International Conference on Innovation, Communication and Engineering, ICICE 2019, Zhengzhou, Henan Province, China, 25/10/19. https://doi.org/10.1109/ICICE49024.2019.9117552

Increasing PE Utilization with a SW/HW Co-Design Technique for Sparse Convolutional Neural Networks. / Tseng, Wei Fan; Lai, Bo Cheng; Pan, Jyun Wei.
Proceedings of the 2019 8th International Conference on Innovation, Communication and Engineering, ICICE 2019. ed. / Shoou-Jinn Chang; Sheng-Joue Young; Artde Donald Kin-Tak Lam; Liang-Wen Ji; Hao-Ying Lu; Stephen D. Prior. Institute of Electrical and Electronics Engineers Inc., 2019. p. 74-77 9117552 (Proceedings of the 2019 8th International Conference on Innovation, Communication and Engineering, ICICE 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Increasing PE Utilization with a SW/HW Co-Design Technique for Sparse Convolutional Neural Networks

AU - Tseng, Wei Fan

AU - Lai, Bo Cheng

AU - Pan, Jyun Wei

PY - 2019/10

Y1 - 2019/10

N2 - Pruning convolution neural networks (CNN) has proved to be an effective technique to decrease the network size without loss of accuracy. By processing the compressed format of the network, the energy consumption can be considerably reduced. However, the existing SIMD-like sparse CNN accelerator suffers from low processing engine (PE) utilization due to the irregular distribution of effectual pairs. In this paper, we address this issue by proposing a software and hardware codesign technique, including a novel data compression scheme and a dedicated module to handle this compressed format. When compared to a state-of-the-art SIMD-like accelerator, the proposed co-design technique can reduce the computation time of conv3, conv4, conv5 of AlexNet by 15%, 33%, 31%.

AB - Pruning convolution neural networks (CNN) has proved to be an effective technique to decrease the network size without loss of accuracy. By processing the compressed format of the network, the energy consumption can be considerably reduced. However, the existing SIMD-like sparse CNN accelerator suffers from low processing engine (PE) utilization due to the irregular distribution of effectual pairs. In this paper, we address this issue by proposing a software and hardware codesign technique, including a novel data compression scheme and a dedicated module to handle this compressed format. When compared to a state-of-the-art SIMD-like accelerator, the proposed co-design technique can reduce the computation time of conv3, conv4, conv5 of AlexNet by 15%, 33%, 31%.

KW - Machine learning

KW - SIMD architecture

KW - Sparse convolution neural networks

UR - https://www.scopus.com/pages/publications/85094664208

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DO - 10.1109/ICICE49024.2019.9117552

M3 - Conference contribution

AN - SCOPUS:85094664208

T3 - Proceedings of the 2019 8th International Conference on Innovation, Communication and Engineering, ICICE 2019

SP - 74

EP - 77

BT - Proceedings of the 2019 8th International Conference on Innovation, Communication and Engineering, ICICE 2019

A2 - Chang, Shoou-Jinn

A2 - Young, Sheng-Joue

A2 - Lam, Artde Donald Kin-Tak

A2 - Ji, Liang-Wen

A2 - Lu, Hao-Ying

A2 - Prior, Stephen D.

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 8th International Conference on Innovation, Communication and Engineering, ICICE 2019

Y2 - 25 October 2019 through 30 October 2019

ER -

Tseng WF, Lai BC, Pan JW. Increasing PE Utilization with a SW/HW Co-Design Technique for Sparse Convolutional Neural Networks. In Chang SJ, Young SJ, Lam ADKT, Ji LW, Lu HY, Prior SD, editors, Proceedings of the 2019 8th International Conference on Innovation, Communication and Engineering, ICICE 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 74-77. 9117552. (Proceedings of the 2019 8th International Conference on Innovation, Communication and Engineering, ICICE 2019). doi: 10.1109/ICICE49024.2019.9117552

Increasing PE Utilization with a SW/HW Co-Design Technique for Sparse Convolutional Neural Networks

Abstract

Publication series

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UN SDGs

Keywords

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