Increasing PE Utilization with a SW/HW Co-Design Technique for Sparse Convolutional Neural Networks

Wei Fan Tseng, Bo Cheng Lai, Jyun Wei Pan

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Pruning convolution neural networks (CNN) has proved to be an effective technique to decrease the network size without loss of accuracy. By processing the compressed format of the network, the energy consumption can be considerably reduced. However, the existing SIMD-like sparse CNN accelerator suffers from low processing engine (PE) utilization due to the irregular distribution of effectual pairs. In this paper, we address this issue by proposing a software and hardware codesign technique, including a novel data compression scheme and a dedicated module to handle this compressed format. When compared to a state-of-the-art SIMD-like accelerator, the proposed co-design technique can reduce the computation time of conv3, conv4, conv5 of AlexNet by 15%, 33%, 31%.

Original languageEnglish
Title of host publicationProceedings of the 2019 8th International Conference on Innovation, Communication and Engineering, ICICE 2019
EditorsShoou-Jinn Chang, Sheng-Joue Young, Artde Donald Kin-Tak Lam, Liang-Wen Ji, Hao-Ying Lu, Stephen D. Prior
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages74-77
Number of pages4
ISBN (Electronic)9781728158396
DOIs
StatePublished - Oct 2019
Event8th International Conference on Innovation, Communication and Engineering, ICICE 2019 - Zhengzhou, Henan Province, China
Duration: 25 Oct 201930 Oct 2019

Publication series

NameProceedings of the 2019 8th International Conference on Innovation, Communication and Engineering, ICICE 2019

Conference

Conference8th International Conference on Innovation, Communication and Engineering, ICICE 2019
Country/TerritoryChina
CityZhengzhou, Henan Province
Period25/10/1930/10/19

Keywords

  • Machine learning
  • SIMD architecture
  • Sparse convolution neural networks

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